◆PR375 ◇invited42 ★award42 #pat.63

----2027-----------------------------------------------------------------------------------------------------

◇Yasuhiko Nakashima: "The Way to CGLA: CPU Grounded Linear Array", ASP-DAC2026 invited talk, Jan. (2027)

◆Koki Asahina, Dohyun Kim, Yasuhiko Nakashima: "IMAX-SpMM: An Energy-Efficient and Dataflow-Optimized SpMM Kernel on CGLA for GNNs", IEICE Trans., Vol.E110-D,No.01,pp.-,Jan. (2027)

----2026-----------------------------------------------------------------------------------------------------

◆Hikaru Okamoto, Vu Trung Duong Le, Van Tinh Nguyen, Hoai Luan Pham, Yasuhiko Nakashima: "MMzk-D128: A High-Throughput DMA-128-Aware 384-bit Montgomery Multiplier on SoC FPGA for zk-SNARK", Concurrency and Computation: Practice and Experience, Dec. (2026)

◇Yasuhiko Nakashima: "The Road to CGLA — What We Learned and What Comes Next", CANDAR2026 keynote, Nov. (2026)

◇Yasuhiko Nakashima: "From Training Engineers to Future Accelerators – The Road to CGLA", ICSEC2026 invited talk, Nov. (2026)

◆Jiratha Wongsomboon, Varunya Attasena, Thitipong Satiramatekul, Yirong Kan, Yasuhiko Nakashima: "Energy-Efficient Multimodal Emotion Recognition via Late Fusion on Edge FPGA", ICSEC2026, Nov, (2026)

◆Daran Jankhuntos, Varunya Attasena, Thitipong Satiramatekul, Yirong Kan, Yasuhiko Nakashima: "Energy-Efficient FPGA-Based for Real-Time Object Detection on Edge Devices", ICSEC2026, Nov, (2026)

◆Takuto Ando, Yasuhiko Nakashima: "Mamba-Family State-Space Model Kernels on a Programmable CGLA", 19th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2026), Dec. (2026)

◆Van Duy Tran, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima: "DMPGE: A Scalable and Efficient FPGA Quantum Emulator Based on Distributed Memory and Parallel Gate Execution", CSA Workshop in conjunction with CANDAR 2026, Nov. (2026)

◆Long Hau Huynh, Chi Cong Ho, Hoai Luan Pham, Vu Trung Duong Le, Quang Phuong Nguyen, Shu-Yu Chou, Shanq-Jang Ruan, Yasuhiko Nakashima: "ASB-AP-BWE: Phase-Aware Speech Bandwidth Extension with Invocation-Specific Mixed-Precision Inference and Memory-Bounded Real-Time Streaming on Edge Platforms", CSA Workshop in conjunction with CANDAR 2026, Nov. (2026)

◆Takuto Ando, Yasuhiko Nakashima: "Implementation and Evaluation of BitNet Inference on a CGLA by Signed-Int4 Instructions", CSA Workshop in conjunction with CANDAR 2026, Nov. (2026)

◆Takuto Ando, Yasuhiko Nakashima: "Implementation and Evaluation of NTT Arithmetic for ML-KEM on a CGLA", WICS Workshop in conjunction with CANDAR 2026, Nov. (2026)

◆Gia Lam Huynh, Ngoc Huy Nguyen, Vu Trung Duong Le, Anh Kiet Pham, Van Tinh Nguyen, Hoai Luan Pham, Yasuhiko Nakashima: "DFE-SoC: Power-Efficient 32-PE LSTM Accelerator for Robotic Catching on FPGA SoC", PDAA Workshop (poster) in conjunction with CANDAR 2026, Nov. (2026)

◆Tran Le Xuan Hieu, Vu Tuan Hai, Le Vu Trung Duong, Pham Hoai Luan and Yasuhiko Nakashima: "CG-GLORE: A Conjugate Gradient–Based Global-Local Regularization Network for Sparse-View CT Reconstruction", The 37th British Machine Vision Conference (BMVC 2026), Nov. (2026)

◆Van Duy Tran, Tuan Hai Vu, Hoai Luan Pham, Cao Doanh Bui, Vu Trung Duong Le, Yasuhiko Nakashima: "HPQEA: A Scalable FPGA-Based High-Performance Quantum Emulator with Parallel Architecture and High-Bandwidth Memory Optimization", Concurrency and Computation: Practice and Experience, Nov. (2025)

◆Luo Qiao, Renyuan Zhang, Yasuhiko Nakashima, Yirong Kan, Hang Jin: "A Low-Power Multi-Radix Accumulation Architecture for 225-Way INT8 MAC Computation", IEEE GCCE 2026, Oct. (2026)

◆Yuchang Huang, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "A Lightweight Hierarchical Spike Attention Mechanism for Surface EMG Gesture Recognition", IEEE GCCE 2026, Oct. (2026)

◆Tianyu Liu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "Teacher-Guided Saliency Refinement for Low-Bit Spiking Quantization of Large Language Models", IEEE GCCE 2026, Oct. (2026)

◆Takuto Ando, Ayumu Takeuchi, Yu Eto, Yasuhiko Nakashima: "Design and Evaluation of Energy-Efficient Whisper Dot-Product Kernel Offloading on a CGLA Architecture", Concurrency and Computation: Practice and Experience, DOI:10.1002/cpe.70826, Aug. (2026)

◆Mutsumi Kimura, Yuji Miyato, Michihiro Shintani, Mami Fujii, Yusaku Magari, Hidenori Kawanishi, Tokiyoshi Matsuda, Juan Paolo S. Bermundo, Takanori Takahashi, Yukiharu Uraoka, Takumi Kuwahara, Reon Oshio, Yasuhiko Nakashima, Yi-Chien Chen, Chung-Tien Chiu, Chih-Lung Lin: "Amorphous metal-oxide semiconductor thin-film neuron, synapse, and neuromorphic system", Scientific Reports, Aug. (2026)

◆Pham Thien Long Dinh, Anh Kiet Pham, Vu Trung Duong Le, Hai Tuan Vu, Trong Nhan Le, Minh Triet Vu, Yasuhiko Nakashima: "A Compact Karatsuba Accelerator for HQC on FPGA-Based IoT Devices", IAAA'2026, Jul. (2026)

◆Tran Le Xuan Hieu, Vu Tuan Hai, Le Vu Trung Duong, Pham Hoai Luan and Yasuhiko Nakashima: "PACOX: A FPGA-based Pauli Composer Accelerator for Pauli String Computation", IEEE Symposium on Low-Power and High-Speed Chips 2026, Apr. (2026)

◆Anh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu, Hoai Luan Pham, Van Tinh Nguyen and Yasuhiko Nakashima: "Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security", IEEE Symposium on Low-Power and High-Speed Chips 2026, Apr. (2026)

◆Ryo Maeda, Thi Hong Tran, Vu Trung Duong Le, Anh Kiet Pham, Van Tinh Nguyen and Yasuhiko Nakashima: "CFX: A Conflict-Free and Exponent-Scaled FFT/IFFT Accelerator on FPGA SoC for Energy-Efficient Edge Computing", IEEE Symposium on Low-Power and High-Speed Chips 2026, Apr. (2026)

◆Jiajun Zhong, Vu Trung Duong Le, Hoai Luan Pham and Yasuhiko Nakashima: "Spikceiver: Compact Audio-Visual Spiking Transformer with Depthwise Splitting and Bottleneck Attention", IEEE Symposium on Low-Power and High-Speed Chips 2026, Apr. (2026)

◆Yiling Yang, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "Mutual Information Loss for Enhancing Class-Wise Representation in Spiking Neural Networks", 2026 IEEE International Symposium on Circuits and Systems (ISCAS), May. (2026) 

◆Haoyu Tang, Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima: "DystoHD: An Area-Efficient Hyperdimensional Computing System with Dynamic Hypervector Generation for Memory-Constrained Devices", The Journal of Supercomputing, Mar. (2026) 

◆★Best Paper Award★Takuto Ando, Ayumu Takeuchi, Yu Eto, Yoshifumi Munakata, Yasuhiko Nakashima: "Q-Snap: Quantization-Aware Dynamic Chunking for LLM Execution on a CGLA", International Conference on Intelligent Systems and Networks, Mar. (2026)

◆Doanh C. Bui, Ba Hung Ngo, Pham Hoai Luan, Khang Nguyen, Mai K. Nguyen, Yasuhiko Nakashima: "MergeSlide: Continual Model Merging and Task-to-Class Prompt-Aligned Inference for Lifelong Learning on Whole Slide Images", The IEEE/CVF Winter Conference on Applications of Computer Vision 2026 (WACV 2026), Mar. (2026)

◆Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "Efficient Hardware Implementation of Robust Binary Neural Networks Using End-to-End Unipolar Representation", IEICE Trans., Vol.E109-A, No.3, Mar. (2026)

◆Le Vu Trung Duong, Hoai Luan Pham, Tran Van Duy, Yasuhiko Nakashima: "UniCrypt-Ultra: A 64-bit Quad-Core Universal Cryptographic Engine for Multi-mode Cryptographic Processing in Blockchain IoT and Society 5.0", IEEE Micro, MicroSI-2025-08-0075.R1, Feb. (2026)

◆Mingyang Li, Yirong Kan, Man Wu, Renyuan Zhang, and Yasuhiko Nakashima: "FPSpike: A Fully-Parallel and Reconfigurable Architecture for Accelerating Spiking Neural Networks with Structured Sparsity", IEEE Trans. on Circuits and Systems I, Jan. (2026)

◆Binh Ngoc Thanh Bui, Hoai Luan Pham, Vu Trung Duong Le, Hai Tuan Vu, Yasuhiko Nakashima: "A Protocol-Aware P4 Pipeline for MQTT Security and Anomaly Mitigation in Edge IoT Systems", ICOIN 2026, Jan. (2026)

◆Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "An FPGA Accelerator for Vision Transformer with Quantization and LUT-Based Operations", IEICE Trans., Vol.E109-D, No.1, pp.41-48, Jan. (2026)

◆Kazuki Sawai, Riku Horio, Rodrigo Vieira Witt, Tokiyoshi Matsuda, Hidenori Kawanishi, Takaaki Miyasako, Sanggyu Koh, Tadasu Hosokura, Reon Oshio, Takumi Kuwahara, Yasuhiko Nakashima, and Mutsumi Kimura: "Hardware Emulation of Membrane Potential Using a 1T1C FeFET–Capacitor Structure for Neuromorphic Applications", IEEE Transactions on Electron Devices, Jan. (2026)

----2025-----------------------------------------------------------------------------------------------------

◆Takuto Ando, Yu Eto, Yasuhiko Nakashima: "Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA", IEEE Access, Dec. (2025)

◆Cao Doanh Bui, Hoai Luan Pham, Vu Trung Duong Le, K. Mai Nguyen, Yasuhiko Nakashima: "Merging-based Federated Learning for Lifelong Whole Slide Image Analysis with Vision-Language Models", 14th International Symposium on Information and Communication Technology (SOICT 2025), Dec. (2025)

◆Takuto Ando, Yu Eto, Yasuhiko Nakashima: "Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator", 18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2025), Dec. (2025)

◆★Best Paper Award★ Takuto Ando, Yu Eto, Ayumu Takeuchi, Yasuhiko Nakashima: "Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA", CANDAR'25 regular paper, Nov. (2025)

◆Thanh Hai To, Vu Trung Duong Le, Van Tinh Nguyen, Van Tuan Luu, Pham Hoai Luan, Yasuhiko Nakashima: "zk-STARKs in Action: Real-Time and Post-Quantum Verification for Banking Transactions", CANDAR'25 WICS regular paper, Nov. (2025)

◆Tuan Hai Vu, Cao Doanh Bui, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima: "Transfer-Based Strategies for Multi-Target Quantum Optimization", CANDAR'25 PDAA regular paper, Nov. (2025)

◆Hikaru Okamoto, Vu Trung Duong Le, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima: "MMzk: 384-bit Low-Resource Montgomery Multiplier on FPGA for zk-SNARK", CANDAR'25 regular paper, Nov. (2025)

◆Van Duy Tran, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Cao Doanh Bui, Yasuhiko Nakashima: "HPQEA: A Scalable and High-Performance Quantum Emulator with High-Bandwidth Memory for Diverse Algorithms Support", CANDAR'25 regular paper, Nov. (2025)

◆Takumi Kuwahara, Reon Oshio, Taiga Hirano, Mutsumi Kimura, Yasuhiko Nakashima: "Ultra Low Latency Spiking Locally Competitive Algorithm for Spatio-temporal Data and Hierarchical Networks", CANDAR'25 regular paper, Nov. (2025)

◆Takumi Kuwahara, Reon Oshio, Renyuan Zhang, Mutsumi Kimura, and Yasuhiko Nakashima: "Fusion Synapse by Memristor and Capacitor for Spiking Neuromorphic Systems - Dramatical Reduction in Circuit Area -", The 32nd International Conference on Neural Information Processing, ICONIP 2025, Nov. (2025)

◆★Young Researcher Award★ Takuto Ando, Yu Eto, Yasuhiko Nakashima: "A Detailed Analysis of LLM Execution on IMAX3 and Initial Evaluation of IMAX4 Prototype for Server Environment", Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Oct. (2025)

◆Takuto Ando, Yasuhiko Nakashima: "Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels", IEEE International System-On-Chip Conference (SOCC2025) (poster), Sep. (2025)

◆Yu Eto, Yasuhiko Nakashima: "LLM Performance Bottlenecks on CGLA", IEEE International System-On-Chip Conference (SOCC2025) (poster), Sep. (2025)

◆Ayumu Takeuchi, Yasuhiko Nakashima: "Energy-Efficient FlashAttention Acceleration on CGLA", IEEE International System-On-Chip Conference (SOCC2025) (poster), Sep. (2025)

◆Ayumu Takeuchi, Yasuhiko Nakashima: "Power Efficient Attention Acceleration on CGLA", IEEE International System-On-Chip Conference (SOCC2025), Sep. (2025)

◆Yu Eto, Takuto Ando, Yasuhiko Nakashima: "Performance Evaluation of Flan-T5 in CGLA Based Accelerators", IEEE International System-On-Chip Conference (SOCC2025), Sep. (2025)

◆Yirong Kan, Guangxian Zhu, Renyuan Zhang, Yasuhiko Nakashima: "A DNN-Oriented Rapid Simulation Framework for Digital Processing-in-Memory Architectures", IEEE International System-On-Chip Conference (SOCC2025), Sep. (2025)

◆Doanh C. Bui, Pham Hoai Luan, Vu Trung Duong Le, Yasuhiko Nakashima: "Predicting Biochemical Recurrence of Prostate Cancer from Whole-Slide Images: a Benchmark of Pathology Foundation Models", EIDT 2025, Sep. (2025)

◆Doanh C. Bui, Pham Hoai Luan, Vu Trung Duong Le, Vu Tuan Hai, Van Duy Tran, Yasuhiko Nakashima: "ZeroSlide: Is Zero-Shot Classification Adequate for Lifelong Learning in Whole-Slide Image Analysis in the Era of Pathology Vision-Language Foundation Models?", MICCAI 2025 Workshop MSB EMERGE, Sep. (2025)

◆Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, and Yasuhiko Nakashima: "Benchmarking variants of the Adam optimizer for Quantum Machine Learning Applications", IEEE Open Journal of the Computer Society, Aug. (2025)

◆Doanh Cao Bui, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, and Yasuhiko Nakashima: "ADaFSlide: Adapting Vision-Language Foundation Model for Lifelong Whole Slide Image Analysis", IEEE R10 HTC 2025, Sep. (2025)

◆Dohyun Kim and Yasuhiko Nakashima: "Optimizing Matrix-Vector Operations with CGLA for High-Performance Approximate k-NN Search", IEEE Access, Aug. (2025)

◆Doanh Cao Bui, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Khang Nguyen, and Yasuhiko Nakashima: "Lifelong Whole Slide Image Analysis: Online Vision-Language Adaptation and Past-to-Present Gradient Distillation", IEEE Access, Aug. (2025)

◇中島康彦, 桑原拓海, 青木尊, 押尾怜穏, 木村睦: "デジタルとキャパシタの協調による推論システム", 信学技報, CPSY2025, Jun. (2025)

◆Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, and Yasuhiko Nakashima: "FQsun: A Configurable Wave Function-Based Quantum Emulator for Power-Efficient Quantum Simulations", IEEE Access, Aug. (2025)

◆Van-Tuan Luu, Hoai Luan Pham, Van Tinh Nguyen, Van-Phuc Hoang, Nguyen Van Trung, Vu Trung Duong Le and Yasuhiko Nakashima: "Correlation Power Analysis of Pipelined and Multi-Threaded Coarse-Grained Reconfigurable Cryptographic Accelerator", ICDV 2025, Jun. (2025)

◆Duy Tran Van, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, and Yasuhiko Nakashima: "QEA: An Accelerator for Quantum Circuit Simulation with Resources Efficiency and Flexibility", ICDV 2025, Jun. (2025)

◆Hoai Luan Pham, Thi Diem Tran, Vu Trung Duong Le, Tuan Hai Vu, and Yasuhiko Nakashima: "A Fast and Memory-Efficient CNN Accelerator for ECG Classification in Remote Healthcare Systems", The 22nd International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2025), May. (2025)

◆Hoai Luan Pham, Thi Diem Tran, Vu Trung Duong Le, and Yasuhiko Nakashima: "MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices", IEEE Transactions on Circuits and Systems I: Regular Papers. pp.1-14, May. (2025)

◆★Featured Poster Award★ Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "Pattern-Aware Encoding Scheme for Parameter Compression of Binary Neural Networks", IEEE Symposium on Low-Power and High-Speed Chips 2025 (poster), Apr. (2025)

◆Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran and Yasuhiko Nakashima: "UniCrypt: Universal Crypto Engine with Optimized Resource Sharing for Security Applications", IEEE Symposium on Low-Power and High-Speed Chips 2025, Apr. (2025)

◆Nastaran Asadi, Babak Golbabaei, Yirong Kan, Renyuan Zhang and Yasuhiko Nakashima: "A Lightweight Transformer Model With Dynamic Sparse Mask for Neural Machine Translation", IEEE Symposium on Low-Power and High-Speed Chips 2025, Apr. (2025)

◆★Best Paper Award★ Yu Eto, Yasuhiko Nakashima: "Implementation and Performance Analysis of LLaMA on a CGLA", International Conference on Intelligent Systems and Networks (ICISN), Mar. (2025)

◆Koki Asahina, Dohyun Kim, Tomoya Akabe, Vu Trung Duong Le, Yasuhiko Nakashima: "Energy-Efficient SpMM Kernels for GATs and GCNs on a CGLA", 2nd International Conference on Machine Learning and Autonomous Systems (ICMLAS), Mar. (2025)

◆Duong Thi Sang, Ren Imamura, Tomoya Akabe and Yasuhiko Nakashima: "Energy Consumption Optimization of Multi-dimensional U-Nets on CGLA", IEEE Access, Feb. (2025)

◆Reon Oshio, Takumi Kuwahara, Takeru Aoki, Mutsumi Kimura, and Yasuhiko Nakashima: "Neuromorphic system using capacitor synapses", Scientific Reports, Vol.15, 3954, DOI: 10.1038/s41598-025-87924-6, Jan. (2025)

◆Tomoya Akabe, Vu Trung Duong Le and Yasuhiko Nakashima: "IMAX: A Power-efficient Multilevel Pipelined CGLA and Applications", IEEE Access, 10.1109/ACCESS.2024.3524415, Jan. (2025)

----2024-----------------------------------------------------------------------------------------------------

◆Hoai Luan Pham, Hai Hau Nguyen, Vu Trung Duong Le, Tuan Hai Vu, Thi Diem Tran, Thi Hong Tran and Yasuhiko Nakashima: "MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements", IEEE MICRO, Dec. (2024)

◆Vu Tuan Hai, Le Vu Trung Duong, Pham Hoai Luan, Yasuhiko Nakashima: "Efficient Random Quantum Circuit Generator: A Benchmarking Approach for Quantum Simulators", 2024 RIVF International Conference on Computing and Communication Technologies, Dec. (2024)

◇Yasuhiko Nakashima: "指令塔＝高度アーキテクトの育成レシピ", 政策アクション会議2024, Dec. (2024)

◇Yasuhiko Nakashima: "ここから未来を創る！～シンプルな部品から最先端テクノロジーへの挑戦～", 生駒市中学生向けセミナー2024, Dec. (2024)

◆Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Van Duy Tran, Tuan Hai Vu, and Yasuhiko Nakashima: "CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. (2024)

◆Tran Xuan Hieu Le, Hoai Luan Pham, Hai Vu Tuan, Vu Trung Duong Le and Yasuhiko Nakashima: "Theoretical Analysis of the Memory-Efficient Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs", 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2024), Kuala Lumpur, Malaysia, Dec. (2024)

◆★Best Paper Award★ Hai Hau Nguyen, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Le Vu Trung Duong, Duc Khai Lam and Yasuhiko Nakashima: "Hator: A High-Efficiency CGRA-Based 32/64-Bit Hashing Accelerator with Real-Time Performance Analysis", 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2024), Kuala Lumpur, Malaysia, Dec. (2024)

◆Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Yasuhiko Nakashima: "A Directly-Trained Spiking Locally Competitive Algorithm for Ultra-Fast LASSO Solver", The 31st International Conference on Neural Information Processing (ICONIP2024), Dec. (2024)

◆Vu Trung Duong Le, Anh Kiet Pham, Hoai Luan Pham, Tuan Hai Vu, Yasuhiko Nakashima: "OSA: FPGA-based Octa-core SPHINCS+ Accelerator for IoT Security Applications", SOICT 2024, Dec. (2024)

◆Hitoaki Uetani, Yasuhiko Nakashima: "Implementation and Evaluation of LLM on a CGLA", CANDAR'24 regular paper, Nov. (2024)

◆Vu Tuan Hai, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima: "Benchmarking Classical and Quantum Optimizers for Quantum Simulator", CANDAR'24 regular paper, Nov. (2024)

◆Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "An FPGA-Oriented Quantization Approach for Vision Transformer with LUT-Friendly Operations", CANDAR'24 regular paper, Nov. (2024)

◆Vu Trung Duong Le, Anh Kiet Pham, Hoai Luan Pham, Tuan Hai Vu, Yasuhiko Nakashima: "PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC", CANDAR'24 regular paper, Nov. (2024)

◆Van Duy Tran, Tran Xuan Hieu Le, Thi Diem Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Tinh Nguyen, Yasuhiko Nakashima: "Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation", CANDAR'24 GCA regular paper, Nov. (2024)

◆Thi Diem Tran, Ngoc Quoc Tran, Thi Thu Khiet Dang, Hoai Luan Pham, Yasuhiko Nakashima: "ECG Captioning with Prior-Knowledge Transformer and Diffusion Probabilistic Model", Journal of Healthcare Informatics Research, Oct. (2024)

◇Yasuhiko Nakashima: "情報インフラの暗い未来 AI/BCと食料，2択ならどうする?", 生駒市公開講座2024, Oct. (2024)

◆Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima, Wenhui Luo, Naoki Takeuchi, Nobuyuki Yoshikawa and Olivia Chen: "SuperSIM: A comprehensive benchmarking framework for neural networks using superconductor josephson devices", Journal of Superconductor Science and Technology, vol.27, no.9, Aug. (2024)

◆Vu Tuan Hai, Le Vu Trung Duong, Pham Hoai Luan, and Yasuhiko Nakashima: "Efficient Parameter-Shift Rule Implementation for Computing Gradient on Quantum Simulators", Asian Conference on Quantum Information Science, AQIS, poster, Aug. (2024)

◆Yuma Ishisaki, Reon Oshio, Takumi Kuwahara, Michihiro Shintani, Eisuke Tokumitsu, Tokiyoshi Matsuda, Hidenori Kawanishi, Yasuhiko Nakashima, Mutsumi Kimura: "Analog Memcapacitor by Ferroelectric Capacitor and its Application to Spiking Neuromorphic System", IEEE Transactions on Electron Devices, Vol.71, Issue 8, pp.4626-4630, DOI: 10.1109/TED.2024.3408783, Aug. (2024)

◆Nguyen Dinh Nhat, Pham Hoai Luan, Vu Tuan Hai, Le Vu Trung Duong, Tran Van Duy, and Yasuhiko Nakashima: "A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security Applications", IEEE 21st International SoC Conference (ISOCC 2024) (poster), Aug. (2024)

◆Vu Tuan Hai, Vo Minh Kiet, Le Vu Trung Duong, Pham Hoai Luan, Le Bin Ho, and Yasuhiko Nakashima: "Quantum Battery Optimization through Quantum Machine Learning Techniques", IEEE 21st International SoC Conference (ISOCC 2024), Aug. (2024)

◆★Telechips Award★ Nguyen Ngoc Hung, Le Duc Hong An, Le Vu Trung Duong, Nguyen Van Tinh, Vu Tuan Hai, Tran Van Duy, Pham Hoai Luan, and Yasuhiko Nakashima: "LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography", IEEE 21st International SoC Conference (ISOCC 2024), Aug. (2024)

◆Le Vu Trung Duong, Pham Hoai Luan, Vu Tuan Hai, Tran Van Duy, Tran Thi Diem, and Yasuhiko Nakashima: "UCP: A Unified Cryptographic Processor for High Performance and Low Power Security Applications", IEEE 21st International SoC Conference (ISOCC 2024), Aug. (2024)

◆Pham Hoai Luan, Le Vu Trung Duong, Vu Tuan Hai, Tran Van Duy, and Yasuhiko Nakashima: "CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain Mining", IEEE 21st International SoC Conference (ISOCC 2024), Aug. (2024)

◆Le Duc Hong An, Le Vu Trung Duong, Ho Viet Anh, Vu Tuan Hai, Nguyen Van Tinh, Pham Hoai Luan, and Yasuhiko Nakashima: "High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications", IEEE 21st International SoC Conference (ISOCC 2024), Aug. (2024)

◆Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Renyuan Zhang and Yasuhiko Nakashima: "Fusion Synapse by Memristor and Capacitor for Spiking Neuromorphic Systems", Neurocomputing, vol.593, 127792, DOI: 10.1016/j.neucom.2024.127792, Aug. (2024)

◆Hoai Luan Pham, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, and Yasuhiko Nakashima: "LiCryptor: High-speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography", IEEE Transactions on Circuits and Systems I: Regular Papers. pp.1-14, Jul. (2024)

◆Dinh Nhat Nguyen, Van Duy Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Duc Khai Lam, Thi Hong Tran and Yasuhiko Nakashima: "HyperNTT: A Fast and Accurate NTT/INTT Accelerator with Multi-Level Pipelining and an Improved K2-RED Module", ITC-CSCC2024, Okinawa, Jul. (2024)

◆Vu Truc Quynh, Vu Tuan Hai, Le Vu Trung Duong, Pham Hoai Luan and Yasuhiko Nakashima: "A Quantum Circuit Design for Quantum Portfolio Optimization Problem", ITC-CSCC2024, Okinawa, Jul. (2024)

・Yasuhiko Nakashima: "IMAX3でchat.pyが動くまでにわかったこと", 信学技報, CPSY2024-6, pp.30-35, Jun. (2024)

◆Mingyang Li, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections", IEEE International Symposium on Circuits & Systems, May. (2024)

◆Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang and Yasuhiko Nakashima: "Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays", IEEE Symposium on Low-Power and High-Speed Chips 2024, Apr. (2024)

◆Hoai Luan Pham, Hai Hau Nguyen, Vu Trung Duong Le, Tuan Hai Vu, Thi Diem Tran, Thi Hong Tran and Yasuhiko Nakashima: "MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements", IEEE Symposium on Low-Power and High-Speed Chips 2024, Apr. (2024)

◇Yasuhiko Nakashima et al.: "Exploring the Potential, Limitations, and Challenges of PiM (Processing-in-Memory) and CiM (Computation-in-Memory)", IEEE Symposium on Low-Power and High-Speed Chips 2024 Panel session, Apr. (2024)

◇Yasuhiko Nakashima: "IMAX3: An Alternative Approach to Green PiM", GX実現に向けた異分野連携シンポジウム, Osaka, Apr. (2024)

◇Yasuhiko Nakashima: "IMAX3: An Alternative Approach to Green PiM", Green and Low Carbon Computing Seminar, Yokohama, Apr. (2024)

◇Yasuhiko Nakashima: "IMAX3: An Alternative Approach to Green PiM", 京都クオリアフォーラム, 島津製作所, Apr. (2024)

◆Le Vu Trung Duong, Hoai Luan Pham, Thi Hong Tran, and Y.Nakashima: "Flexible and Energy-efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-based IoT Applications", IEICE Trans., Vol.E107-A, No.3, pp.319-330, Mar. (2024)

◆B.Golbabaei, Y.Kan, R.Zhang, and Y.Nakashima: "Trainig Efficient Stochastic Computing Neural Networks Using One-bit Unipolar Encoding", The 12th RIEC International Symposium on Brain Functions and Brain Computer, Feb. (2024)

◆H.Tang, Y.Kan, R.Zhang, and Y.Nakashima: "A Stochastic Encoding Approach for Robust Brain-Inspired Hyperdimensional Computing", The 12th RIEC International Symposium on Brain Functions and Brain Computer, Feb. (2024)

----2023-----------------------------------------------------------------------------------------------------

◆Ren Imamura, Zhu Guangxian, Sang Duong Thi, Hoai Luan Pham, Renyuan Zhang, and Yasuhiko Nakashima: "Energy-efficient 3D Convolution using Interposed Memory Accelerator eXtension 2 for Medical Image Processing", MICAD'23, Dec. (2023)

◆Sang Duong Thi, Pham Hoai Luan, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima: "Small-footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing", RIVF'23, Dec. (2023)

◆★Outstanding Paper Award★ Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Sang Duong Thi, Yasuhiko Nakashima: "Efficient and High-Speed CGRA Accelerator for Cryptographic Applications", CANDAR'23, Nov. (2023)

◆Sang Duong Thi, Hoai Luan Pham, Le Vu Trung Duong, Diem Thi Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran and Yasuhiko Nakashima: "Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission", IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), Dec. (2023)

◆Le Vu Trung Duong, Hoai Luan Pham, Thi Hong Tran, Sang Duong Thi, Ren Imamura, Akabe Tomoya and Yasuhiko Nakashima: "High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing", IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), Dec. (2023)

◆Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen and Yasuhiko Nakashima: "RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms", IEEE International Conference on Knowledge and Systems Engineering (KSE2023), Oct. (2023)

◆Le Vu Trung Duong, Hoai Luan Pham, Thi Hong Tran, and Y.Nakashima: "Versatile Resource-Shared Cryptographic Accelerator for Multi-Domain Applications", IEEE ICICDT2023, Sep. (2023)

◆Reon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima: "Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing", IEEE International System-On-Chip Conference (SOCC2023), Sep. (2023)

◆Babak Gol Babaei, Guangxian Zhu, Yirong Kan, Zhang Renyuan, Yasuhiko Nakashima: "A Non-Deterministic Training Approach for Memory-Efficient Stochastic Neural Networks", IEEE International System-On-Chip Conference (SOCC2023), Sep. (2023)

◆Sang Thi Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, and Yasuhiko Nakashima: "Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing", SOCC2023, Sep, (2023)

◆Hoai Luan Pham, Vu Trung Duong Le, Sang Thi Duong, Thi Hong Tran, and Yasuhiko Nakashima: "Energy-efficient Unified Multi-hash Coprocessor for Securing IoT Systems Integrating Blockchain", MWCAS2023, Aug, (2023)

◆T. Kuwahara, H. Umemura, M. Kimura, Y. Ishisaki, H. Nishinaka, Y. Nakashima: "Memcapacitor-type Synapse and AC Driving Scheme for Ultra-low Power Consumption Neuromorphic Systems", ICONS2023 (poster), Aug. (2023)

◆Atsushi Sawada, Reon Ochio, Mutsumi Kimura, Rnyuan Zhang, Y.Nakashima: "Spiking Neuromorphic System using Memcapacitors and Pulse Accumulation Circuits", IEICE NOLTA, pp.124-127, Aug. (2023)

◆Mutsumi Kimura, Tanaka Ryo, Isao Horiuchi, Yasushi Hiroshima, and Yasuhiko Nakashima: "Neuromorphic System using Crosspoint-type TaOx/Ta Memristors and Direct Device Training for Associative Memory", IEEE Trans. on Electron Devices, pp.1-6, Jul. (2023)

◆R.Oshio, T.Sugahara, A.Sawada, M.Kimura, R.Zhang, Y.Nakashima: "A Compressed Spiking Neural Network onto Memcapacitive in-Memory Computing Array", IEEE Micro, 0.1109/MM.2023.3285529, Jun. (2023)

◇Y. Nakashima: "IMAX3: Multi-level Pipelined CGRA for Power-efficient +AI Computing", Tutorial: Carbon Neutral Computing for Engineerable AI, AICAS2023, Jun. (2023)

◆Tomoya Akabe, Renyuan Zhang and Yasuhiko Nakashima: "Sensitivity Analysis of Memory Bandwidth on Column-Superposed Versatile Linear CGRA", IEEE Interregional NEWCAS Conference, Jun. (2023)

◆Guangxian Zhu, Yirong Kan, Renyuan Zhang and Yasuhiko Nakashima: "An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability", IEEE Interregional NEWCAS Conference, Jun. (2023)

◆Van-Cam Nguyen, Y. Nakashima: "Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform", IEICE Trans., Vol.E106-D, No.6, Jun. (2023)

◆Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, and Yasuhiko Nakashima: "Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-based IoT Applications", IEEE Design & Test, 10.1109/MDAT.2023.3276936, May, (2023)

★CPSY優秀若手発表賞★ 藤江健吾, 宮川晃輔, 中原博研, 塩谷亮太, 五島正裕, 中島康彦, 津邑公暁: "キャッシュ置き換えアルゴリズムを応用した自動メモ化プロセッサのルックアップテーブル管理手法", 情処研報 Vol.2023-ARC-252，No.40，pp.1-9, Mar. (2023)

◇Y. Nakashima: "IMAX3: Amazing dataflow-centric CGRA and its applications", The 11th RIEC International Symposium on Brain Functions and Brain Computer, Feb. (2023)

・T. Kuwahara, R. Oshio, M. Kimura, R. Zhang, Y. Nakashima: "Combination of memristor and capacitor for synapse device in neuromorphic spiking computing", The 11th RIEC International Symposium on Brain Functions and Brain Computer, Feb. (2023)

・R. Oshio, T. Sugahara, A. Sawada, M. Kimura, R. Zhang, Y. Nakashima: "A memcapacitive spiking neural network with circuit nonlinearity-aware training", The 11th RIEC International Symposium on Brain Functions and Brain Computer, Feb. (2023)

◆Mutsumi Kimura, Shihori Akane, Isao Horiuchi, Yasushi Hiroshima, and Yasuhiko Nakashima: "Phase-Change Memory using Cu2GeTe3 and Multiple Writing Technique for Neuromorphic Systems", IEEE ICCE 2023, Jan. (2023)

----2022-----------------------------------------------------------------------------------------------------

◆Mutsumi Kimura, Yoshinori Miyamae, Mitsuo Tamura, and Yasuhiko Nakashima: "Letter Reproduction from Incomplete Image to Complete Image by Neuromorphic System using LSI Neurons and MOSFET Synapses", Euro Display 2022, Sep. (2022)

◆Mutsumi Kimura, Hiroki Yamanaka, Yasuhiko Nakashima: "Application of Machine Learning to Environmental DNA Metabarcoding", IEEE Access, Sep. (2022)

◆Etsuko Iwagi, Takumi Tsuno, Takahito Imai, Yasuhiko Nakashima, Mutsumi Kimura: "Multilayer Crossbar Array of Amorphous Metal-Oxide Semiconductor Thin Films for Neuromorphic Systems", IEEE Journal of the Electron Devices Society, Vol.10, pp.784-790, Sep. (2022)

◆稲益秀成, 船井遼太郎, 中島康彦: "リニアアレイ型CGRAの高速コンパイルを利用したJIT実行環境の開発", 電子情報通信学会論文誌D, Vol.J105-D, No.12, pp.725-735, Dec. (2022)

◆Chen Yan, Zhang Renyuan, Kan Yirong, Yang Sa, Yasuhiko Nakashima: "Bisection Neural Network Toward Reconfigurable Hardware Implementation", IEEE Transactions on Neural Networks and Learning Systems (TNNLS), Sep. (2022)

◆Man Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights", IEEE International System-on-Chip Conf.(SOCC), Sep. (2022)

◆Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima: "Application and Evaluation of Quantization for Narrow Bit-Width Resampling of Sequential Monte Carlo", IEEE International System-on-Chip Conf.(SOCC), Sep. (2022)

◆Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima: "A Stochastic Coding Method of EEG Signals for Sleep Stage Classification", IEEE International System-on-Chip Conf.(SOCC), Sep. (2022)

◆Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, and Yasuhiko Nakashima: "CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining", IEEE SBCCI2022,Aug. (2022)

◆★Best Track Award on Track SoC, NoC and Reconfigurable Systems★ Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, and Yasuhiko Nakashima: "A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications", IEEE SBCCI2022,Aug. (2022)

◆Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, and Yasuhiko Nakashima: "A High-Efficiency FPGA-Based BLAKE-256 Accelerator for Securing Blockchain Networks", IEEE International Midwest Symposium on Circuits and Systems, Aug. (2022)

◇中島康彦: "CGRAのJITコンパイル化と高機能化の魔法教えます", 回路とシステムワークショップ招待講演, Aug. (2022)

・赤部知也,中島康彦: "主記憶帯域使用率向上のためのCGRAタンデム化", 信学技報, vol.122, no.133, CPSY2022-16, pp.89-92, Jul. (2022)

◆Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, and Yasuhiko Nakashima: "Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator", IEEE Access, Vol.10, pp.68740-68754, Jul. (2022)

◆★Outstanding Effort Award★ 宮川晃輔，中原博研，津邑公暁，中島康彦: "RISC-Vをベースアーキテクチャとする自動メモ化プロセッサの実装および評価", The 6th cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2022), Jul. (2022)

◆Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima: "A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness", IEICE Trans., Vol.E105-D, No.7, Jul. (2022)

◆Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, and Yasuhiko Nakashima: "A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration", CGRA4HPC in conjunction with IPDPS2022, May. (2022)

◆Tomoya Akabe, Hidenari Inamasu, Renyuan Zhang and Yasuhiko Nakashima: "Fusion of Multiple Core and Just-in-Time Compilable CGRA", IEEE Symposium on Low-Power and High-Speed Chips 2022 (poster), Apr. (2022)

◆Ryotaro Funai, Hidenari Inamasu, Renyuan Zhang and Yasuhiko Nakashima: "Evaluation of IMAX2 with Sparse Matrix-matrix Multiplication Units", IEEE Symposium on Low-Power and High-Speed Chips 2022 (poster), Apr. (2022)

◆Reon Oshio, Takuya Sugahara, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang and Yasuhiko Nakashima: "A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training", IEEE Symposium on Low-Power and High-Speed Chips 2022, Apr. (2022)

◆Mutsumi Kimura, Yuki Shibayama, and Yasuhiko Nakashima: "Neuromorphic chip integrated with a large-scale integration circuit and amorphous-metal-oxide semiconductor thin-film synapse devices", Scientific Reports, Apr. (2022)

◆Hiroki Nishimoto, Renyuan Zhang and Yasuhiko Nakashima: "GPGPU Implementation of Variational Bayesian Gaussian Mixture Models", IEICE Trans., Vol.E105-D, No.3, DOI:10.1587/transinf.2021EDP7121, Mar. (2022)

◆Hoai Luan Pham, Tran Thi Hong, Vu Trung Duong Le, and Y.Nakashima: "A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator", IEEE Access, Vol.10, pp.11830-11845, Jan. (2022)

・Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima: "Ternarizing Deep Spiking Neural Network", 信学技報, vol.121, no.343, CPSY2021-30, pp.67-72, Jan. (2022)

・船井遼太朗, 張任遠, 中島康彦: "IMAX2を用いた高効率な疎行列-疎行列積の実装", 信学技報, vol.121, no.343, CPSY2021-25, pp.38-42, Jan. (2022)

----2021-----------------------------------------------------------------------------------------------------

◆Y.Kan, M.Wu, R.Zhang and Y.Nakashima: "MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network", International Symposium on Integrated Circuits and Systems (ISICAS): Session 6-C: Neuromorphic Circuits and Systems, Dec. (2021)

◆Van Tinh NGUYEN, Quang-Kien Trinh, Renyuan Zhang and Yasuhiko Nakashima: "XNOR-BSNN: In-Memory Computing Model for Deep Binarized Spiking Neural Network", IEEE International Conference on High Performance Big Data and Intelligent Systems(HPBD&IS 2021), technical program, Dec. (2021)

◇中島康彦: "非ノイマン型の世界 -CGRAを含む最近の研究紹介-", JEITAデバイス技術分科会招待講演, Nov. (2021)

◆Vu Trung Duong Le, Tran Thi Hong, Hoai Luan Pham, Duc Khai Lam, Y.Nakashima: "MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security", IEEE Access, Vol.9, 10.1109/ACCESS.2021.3131558, Nov. (2021)

◆Van Tinh NGUYEN, Quang-Kien Trinh, Renyuan Zhang and Yasuhiko Nakashima: "STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM", IEEE Access, Vol.9, 10.1109/ACCESS.2021.3125685, Nov. (2021)

◆Reon Oshio, Mutsumi Kimura, and Y. Nakashima: "Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit", CANDAR'21, CSA (Computer Systems and Architectures) workshop, Nov. (2021)

◆Tomoya Akabe, Renyuan Zhang, and Y. Nakashima: "Speeding Up of CGRAs by Reshaping and Stochastic FMA", CANDAR'21, SUSCW (Sustainable Computing Systems) workshop, Nov. (2021)

◆Van Cam Nguyen, Renyuan Zhang, and Y. Nakashima: "Analysis of Fully-Pipelined CNN Implementation on FPGA and HBM2", CANDAR'21, poster, Nov. (2021)

◆Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima: "Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks", IEICE Trans., Vol.E104-D, No.11, DOI:10.1587/transinf.2021EDP7046, Nov. (2021)

◆Man Wu, Yirong Kan, Tati Erlina, Renyuan Zhang, and Y. Nakashima: "DiaNet: An Elastic Neural Network for Effectively Re-configurable Implementation", Elsevier-Journal Neurocomputing, NEUCOM-D-20-04242R2, https://doi.org/10.1016/j.neucom.2021.08.059, Sep. (2021)

◆Kimura Mutsumi, Ishisaki Yuma, Miyabe Yuta, Yoshida Homare, Ogawa Isato, Yokoyama Tomoharu, Haga Ken-ichi, Tokumitsu Eisuke, Nakashima Yasuhiko: "Neuromorphic System using Memcapacitors and Autonomous Local Learning", IEEE Transactions on Neural Networks and Learning Systems: Regular Papers, 10.1109/TNNLS.2021.3106566, Sep. (2021)

◆Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan and Y.Nakashima: "BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks", IEEE Transactions on Circuits and Systems I: Regular Papers, pp.4245-4258, Aug. (2021)

◆Y.Kan, M.Wu, R.Zhang and Y.Nakashima: "MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network", IEEE Transactions on Circuits and Systems I: Regular Papers, 10.1109/TCSI.2021.3099034, Jul. (2021)

◆★Best Student Paper Award★ Tran Thi Diem and Yasuhiko Nakashima: "Exploring Versatility of Primary Visual Cortex Inspired Feature Extraction Hardware Model through Various Network Architectures", 4th International Conference on Computing, Electronics & Communications Engineering, iCCECE'21, Aug. (2021)

◆Van Tinh NGUYEN, T. -K. Luong, E. Popovici, Q. -K. Trinh, Renyuan Zhang and Yasuhiko Nakashima: "An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic", IEEE International Midwest Symposium on Circuits & Systems, pp.386-390, Aug. (2021)

・赤部知也,中島康彦: "シストリックアレイ向け確率的コンピューティングの予備評価", 信学技報, vol.121, no.116, CPSY2021-9, pp.49-52, Jul. (2021)

・澤田篤志, 押尾怜穏, 野村武司, 張任遠, 木村睦, 中島康彦: "メムキャパシタを用いたスパイキングニューラルネットワークの開発", 信学技報, vol. 121, no.116, CPSY2021-11, pp.59-63, Jul. (2021)

◇Yasuhiko Nakashima: "IMAX2: A CGRA with FPU+Multithreading+Chiplet", Panel: Coarse-Grained Reconfigurable Arrays and their Opportunities as Application Accelerators, ASAP2021, invited panel, Jul. (2021)

◇Tomoya Akabe and Hidenari Inamasu: "IMAX2: A CGRA with FPU+Multithreading+Chiplet", ASAP2021 poster, Jul. (2021)

◆Mutsumi Kimura, Yoshinori Miyamae, Mitsuo Tamura and Yasuhiko Nakashima: "Neuromorphic System using LSI Neurons and MOSFET Synapses with Autonomous Learning Rule", ICONS2021 (poster), Jul. (2021)

◆Mutsumi Kimura: "Amorphous-Metal-Oxide-Semiconductor Thin-Film Planar-type Spike-Timing-Dependent-Plasticity Synapse Device", IEEE Electron Device Letters, pp.1014-1016, Jul. (2021)

◆★Outstanding Research Award★ 中原博研，武石隆太郎，津邑公暁，中島康彦: "自動メモ化プロセッサにおける動的利得判定に基づいた適用対象限定手法", xSIG 2021: The 5th. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, Jul. (2021)

◆Tran Thi Diem and Yasuhiko Nakashima: "SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks", IEICE Trans., Vol.E104-C, No.7, pp.319-329, Jul. (2021)

◆Tati Erlina, Renyuan Zhang and Yasuhiko Nakashima: "A Feasibility Study of Multi-Domain Stochastic Computing Circuit", IEICE Trans., Vol.E104-C, No.5, pp.153-163, May. (2021)

◆★Featured Poster Award★ Tomoya Akabe, Mutsumi Kimura, Yasuhiko Nakashima: "Evaluation of Narrow Bit-Width Variation for Training Neural Networks", IEEE Symposium on Low-Power and High-Speed Chips 2021 (poster), Apr. (2021)

◆Tri Dung Phan, Thi Hong Tran, and Yasuhiko Nakashima: "Design and Evaluation of High-performance SHA-3 System on Chip for Society 5.0" IEEE Symposium on Low-Power and High-Speed Chips 2021 (poster), Apr. (2021)

◆Sugahara Takuya, Renyuan Zhang, and Yasuhiko Nakashima: "Training Low-Latency Spiking Neural Network through Knowledge Distillation", IEEE Symposium on Low-Power and High-Speed Chips 2021, Apr. (2021)

◆Van Dai Phan , Hoai Luan Pham , Thi Hong Tran , and Yasuhiko Nakashima: "High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory", IEEE Symposium on Low-Power and High-Speed Chips 2021, Apr. (2021)

◆Tran Thi Hong, Hoai Luan Pham, Yasuhiko Nakashima: "A High-Performance Multimem SHA-256 Accelerator for Society 5.0", IEEE Access, Early Access, DOI:10.1109/ACCESS.2021.3063485, Mar. (2021)

◆Mutsumi Kimura, Ryo Sumida, Ayata Kurasaki, Takahito Imai, Yuta Takishita, and Yasuhiko Nakashima: "Amorphous Metal Oxide Semiconductor Thin Film, Analog Memristor, and Autonomous Local Learning for Neuromorphic Systems", Scientific Reports, Jan. (2021)

・中島康彦: "IMAX2: GTHの8レーン化を契機とするIMAXの倍速化", 信学技報, vol.120, no.338, CPSY2020-27, pp.31-34, Jan. (2021)

・稲益秀成,中島康彦: "シストリックリングアレイ(IMAX2)を用いた高効率誤差逆伝搬の実装", 信学技報, vol.120, no.338, CPSY2020-28, pp.35-39, Jan. (2021)

----2020-----------------------------------------------------------------------------------------------------

◆Taku Honda, Hiroki Nishimoto, Yasuhiko Nakashima: "Speeding Up VBGMM By Using Logsumexp With the Approximate Exp-function", CANDAR'20, poster, Nov. (2020)

◆★CANDAR'20 Outstanding Paper Award★ Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima: "Bayes without Bayesian Learning for Resisting Adversarial Attacks", CANDAR'20, REGULAR PAPER, Nov. (2020)

◆Yuta Takishita, Mutsumi Kimura, and Yasuhiko Nakashima: "Image recognition by implementation of visual cortex and xbar memristor", Proc. International Symposium on Nonlinear Theory and its Applications (NOLTA), Nov. (2020)

◆Van Tinh NGUYEN, T. -K. Luong, Renyuan Zhang and Yasuhiko Nakashima: "A Compact and Accuracy-Reconfigurable Univariate RBF Kernel Based on Stochastic Logic", IEEE International Symposium on Circuits & Systems (poster), Oct. (2020)

◆Ryuta SHINGAI, Yuria HIRAGA, Hisakazu FUKUOKA, Takamasa MITANI, Takashi NAKADA, and Yasuhiko NAKASHIMA: "Construction of an Efficient Divided/Distributed Network Model using Edge Computing", IEICE Trans., Vol.E103-D, No.10, pp.2072-2082, Oct. (2020)

◆★Best Paper Run-up Award★ Renyuan Zhang, Tati Erlina, Tinh Van Nguyen, and Yasuhiko Nakashima: "Hybrid Stochastic Computing Circuits in Continuous Statistics Domain", IEEE Int. System-on-Chip Conf., pp.225-230, Sep. 8th-11th, (2020)

◆★Best Paper Award★ Tran Thi Diem, Mutsumi Kimura and Yasuhiko Nakashima: "Primary Visual Cortex Inspired Feature Extraction Hardware Model", SigTelCom2020, Aug. (2020)

◇中島康彦: "好きなことを靭やかに頑固に素早く", 情報・システムソサイエティ誌 フェローからのメッセージ, Vol.25, No.2, pp.19-20, Aug. (2020)

◆Hoai Luan Pham, Tran Thi Hong, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Y.Nakashima: "Double SHA-256 Hardware Architecture with Compact Message Expander for Bitcoin Mining", IEEE Access, Vol.8, Aug. (2020)

◆Y.Kan, M.Wu, R.Zhang and Y.Nakashima: "A Multi-Grained Reconfigurable Accelerator for Approximate Computing", 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, CYPRUS, Jul. (2020)

◆Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Yasuhiko Nakashima: "An Elastic Neural Network Toward Multi-Grained Re-Configurable Accelerator", The 18th IEEE International NEWCAS Conference, Jun. (2020)

◆Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima: "A Low Complexity Joint Encryption-Modulation Method for IoT Sensor Transceivers", MDPI Circuit and Signal Processing, May. (2020)

◆Dai Phan, Thi Hong Tran and Yasuhiko Nakashima: "SHA-256 Implementation on Coarse-Grained Reconfigurable Architecture", IEEE Symposium on Low-Power and High-Speed Chips 2020 (poster), Apr. (2020)

◆Yuta Takishita1, Masaki Kobayashi1, Kazuki Hattori1, Tokiyoshi Matsuda, Sumio Sugisaki1, Yasuhiko Nakashima, and Mutsumi Kimura: "Memristor property of an amorphous Sn-Ga-O thin-film device deposited using mist chemical-vapor-deposition method", AIP Advances, Vol.10, Issue 3, pp.1-13, https://doi.org/10.1063/1.5143294 DOI: 10.1063/1.5143294, Mar. (2020)

◆Hiroya Ikeda, Hiroki Yamane, Yuta Takishita, Mutsumi Kimura, and Yasuhiko Nakashima: "Influence of characteristic variation of oxide semiconductor and comparison of the activation function in neuromorphic hardware", IEICE Trans. NOLTA, Vol.E11-N, No.2, pp.232-252, Apr. (2020)

◆Jun Iwamoto, Yuma Kikutani, Renyuan Zhang and Yasuhiko Nakashima: "Daisy-chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth", IEICE Trans., Vol.E103-D, No.03, pp.578-589, Mar. (2020)

・中島康彦: "動画認識フロントエンドを想定した特徴抽出専用ハードウェアの構想", 信学技報, vol.119, no.372, CPSY2019-75, pp.147-150, Jan. (2020)

----2019-----------------------------------------------------------------------------------------------------

◆Hoai Luan Pham, Tran Thi Hong and Yasuhiko Nakashima: "Practical Anti-Counterfeit Medicine Management System Based on Blockchain Technology", The 4th IEEE Technology Innovation Management and Engineering Science International Conference (TIMES-iCON2019), Dec. (2019)

◆Tri Dung Phan, Hoai Luan Pham, Duc Khai Lam, Thi Hong Tran, and Yasuhiko Nakashima: "A Decentralized Management Examination System Using Blockchain Technology", IWCCM2019, Dec. (2019)

◆Hiroki Nishimoto, Takashi Nakada and Yasuhiko Nakashima: "GPGPU Implementation of Variational Bayesian Gaussian Mixture Models", CANDAR'19, REGULAR PAPER, Nov. (2019)

◆Van Tinh Nguyen, Tati Erlina, Renyuan Zhang and Yasuhiko Nakashima: "A Programmable Approximate Calculation Unit Employing Time-Encoded Stochastic Computing Elements", Proc. 7'th Int'l Workshop on Computer Systems and Architectures(CSA19), Nov. (2019)

◆Jun Iwamoto, Renyuan Zhang and Yasuhiko Nakashima: "Evaluation of a Chained Systolic Array with High-Speed Links", Proc. 7'th Int'l Workshop on Computer Systems and Architectures(CSA19), Nov. (2019)

◆Dinh Dung Le, Thi Hong Tran and Yasuhiko Nakashima: "Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach", 25th Asia-Pacific Conference on Communications (APCC2019), Nov. (2019)

◆Renyuan Zhang, Yan Chen, Takashi Nakada, and Y. Nakashima: "DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon", IEEE International System-on-Chip Conf.(SOCC), Sep. (2019)

・新谷隆太, 中田尚, 中島康彦: "分散CNNにおける通信効率化のための圧縮技術の比較検討", 信学技報, vol.119, no.147, CPSY2019-36, Jul. (2019)

・本田卓, 岩本淳, 中島康彦: "リニアアレイによる逆行列計算の高速化手法と評価", 情報処理学会研究報告, Vol.2019-ARC-237, No.15, Jul. (2019)

◆M. Kimura, K. Umeda, K. Ikushima, T. Hori, R. Tanaka, J. Shimura, A. Kondo, T. Tsuno, S. Sugisaki, A. Kurasaki, K. Hashimoto, T. Matsuda, T. Kameda, and Y. Nakashima: "Neuromorphic System with Crosspoint-type Amorphous Ga-Sn-O Thin-Film Devices as Self-Plastic Synapse Elements", ECS Trans., Vol. 90, pp.157-166, doi: 10.1149/09001.0157ecst, Jul. (2019)

◆Renyuan Zhang, Takashi Nakada, and Yasuhiko Nakashima: "Programmable Analog Calculation Unit with Multiple Operands: A Solution of Efficient Vector-Computation", IEICE Trans. Fundamentals, Vol.E102-A, No.7, Jul. (2019)

◆Takahiro ICHIKURA, Yuma KIKUTANI, and Yasuhiko NAKASHIMA: "DSA並みの効率を達成するCNNs拡張機能付きCGRAの提案と評価", "A Proposal and Evaluation of a CGRA with CNNs Extension for Near Efficiency to DSA", IEICE Trans., Vol.J102-D, No.07, pp.477-490, Jul. (2019)

◆Yan CHEN, Jing ZHANG, Yuebing XU, Yingjie ZHANG, Renyuan ZHANG, and Yasuhiko Nakashima: "A ReRAM-based Row-column-oriented Memory Architecture for Convolutional Neural Network", IEICE Trans. Electron, Vol.E102-C, No.7, pp.580-584, Jul. (2019)

・中島康彦: "CGLAにおける高速コンパイルとチューニングのためのアーキテクチャ支援", 信学技報, vol.119, no.76, CPSY2019-9, pp.71-76, Jun. (2019)

・西本宏樹,中田尚,中島康彦: "GPGPUを用いた変分混合ガウスモデルのパラメータ推定高速化", 信学技報, vol.119, no.76, CPSY2019-1, pp.1-5, Jun. (2019)

◆★Outstanding Originality Award★ Jun IWAMOTO, Yuma KIKUTANI, Renyuan ZHANG, and Yasuhiko NAKASHIMA: "CGRA Cascading for Narrow Memory Bandwidth and Low Cost", xSIG 2019: The 3rd. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, May. (2019)

◆Hiroya Ikeda, Hiroki Yamane, Yuki Shibayama, Mutsumi Kimura and Yasuhiko Nakashima: "Evaluation of neuromorphic hardware using cellular neural networks and oxide semiconductors", Advances in Parallel and Distributed Computational Models (APDCM2019), May. (2019)

◆Van-Cam NGUYEN, Hoai-Luan PHAM, Tran Thi Hong, Huu Thuan Huynh and Yasuhiko Nakashima: "Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract", IEEE International Conference on Blockchain and Cryptocurrency (ICBC), 10.1109/BLOC.2019.8751256, May, (2019)

◆Tati Erlina, Yan Chen, Renyuan Zhang and Yasuhiko Nakashima: "An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS", GLSVLSI2019, pp.51-56, May. (2019)

◆Sumio Sugisaki, Tokiyoshi Matsuda, Mutsunori Uenuma, Toshihide Nabatame, Yasuhiko Nakashima, Takahito Imai, Yusaku Magari, Daichi Koretomo, Mamoru Furuta, and Mutsumi Kimura: "Memristive characteristic of an amorphous Ga-Sn-O thin-film device", Scientific Reports 9, no2757, Feb. (2019)

◇Yasuhiko Nakashima: "Systolic Arrays as The Last Frontiers", Invited talk in IPB Seminar and UI seminar @ Indonesia, Jan. (2019)

----2018-----------------------------------------------------------------------------------------------------

・新村純平, 生島恵典, 田中遼, 山川大樹, 近藤厚志, 柴山友輝, 津野拓海, 中島康彦, 木村睦: "Ga-Sn-O薄膜を用いたニューラルネットワークの文字認識", 映像情報メディア学会, IDY2018-62, pp.45-48, Dec. (2018)

・柴山友輝, 山川大樹, 生島恵典, 杉崎澄生, 木村睦, 中島康彦: "脳型集積システムのためのIGZO薄膜シナプス", 映像情報メディア学会, IDY2018-63, pp.49-52, Dec. (2018)

◇中島康彦: "AI専用ハードを横目に見ながらやるべきこと", 信学技報, vol.118, no.339, CPSY2018-37, pp.3-8, Dec. (2018)

・西本宏樹, 中田尚, 中島康彦: "変分混合ガウスモデルアクセラレータ設計のための変分推論アルゴリズムの解析", 信学技報, vol.118, no.334, VLD2018-62, pp.155-160, Dec. (2018)

・岩本淳, 菊谷雄真, 中島康彦: "ユニット内フィードバックによるリニアアレイの多重ループ対応手法", 信学技報, vol.118, no.339, CPSY2018-40, pp.33-38, Dec. (2018)

・Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima: "An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit", 信学技報, vol.118, no.339, CPSY2018-41, pp.47-52, Dec. (2018)

◆Dinh Dung Le, Thi Hong Tran and Yasuhiko Nakashima: "Log-Likelihood Ratio Calculation using 3-bit Soft-Decision for Error Correction in Visible Light Communication Systems", IEICE Trans., Vol.E101-A, No.12, pp.2210-2212, Dec. (2018)

◆Hiroya Ikeda, Hiroki Yamane, Yuki Shibayama, Mutsumi Kimura and Yasuhiko Nakashima: "Evaluation of letter reproduction system using cellular neural network and oxide semiconductor synapses by logic simulation", WANC(poster) held in conjunction with CANDAR'18, Takayama, Japan, Dec. (2018)

◆Renyuan Zhang, Noriyuki Uetake, Takashi Nakada and Yasuhiko Nakashima: "Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing", IEEE MICRO, pp.73-82, Dec. (2018)

◆Hoai Luan Pham, Thi-Hong TRAN and Yasuhiko Nakashima: "A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract", IEEE GLOBECOM 2018 Workshops: Blockchain in IoT, Dec. (2018)

◆★Best Paper Award★ Tuan Kiet Tran, Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Huu Thuan Huynh and Yasuhiko Nakashima: "Demonstration of A Visible Light Receiver Using Rolling-Shutter Smartphone Camera", ATC'18, pp.214-219, Oct. (2018)

◆Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Huu-Thuan Huynh, and Yasuhiko Nakashima: "Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver", ATC'18, pp.208-213, Oct. (2018)

◆Dai Long Hoang, Thi Hong Tran and Yasuhiko Nakashima: "Performance Evaluation of 802.11ah Physical Layer Phase Encryption for IoT Applications", ATC'18, pp.84-88, Oct. (2018)

◇中島康彦: "ソザイエティ人図鑑N0.22 中島康彦さん (CPSY研究会)", 情報・システムソサイエティ誌, Vol.23, No.2, pp.4-7, Oct. (2018)

◇Yasuhiko Nakashima: "The End of Normal Computing Era -The Opportunity of Next Generation Computing-", Invited speech in YNU-NAIST Summer Workshop @ Yunnan Univ., Jul. (2018)

◆Daiki Yamakawa, Yuki Shibayama, Hiroki Yamane, Yasuhiko Nakashima, and Mutsumi Kimura: "Cellular Neural Network using IGZO Thin Film as Synapses and LSI as Neurons", AM-FPD 2018, Jul. (to be preesnted) (2018)

◆Keisuke Ikushima, Junpei Shimura, Tokiyoshi Matsuda, Mutsumi Kimura, Hiroki Yamane and Yasuhiko Nakashima: "Research and Development of Ga-Sn-O Thin Films for Application to Neural Networks", AM-FPD 2018, Jul. (to be preesnted) (2018)

◆Ryo Tanaka, Isao Horiuchi, Yukio Mogi, Yasushi Hiroshima, Yasuhiko Nakashima, and Mutsumi Kimura: "Cross-point Device using Ta2O5/Ta Layer for Synapse Element in Neural Network", AM-FPD 2018, Jul. (to be preesnted) (2018)

◆Yuki Shibayama, Daiki Yamakawa, Mutsumi Kimura and Yasuhiko Nakashima: "In-Ga-Zn-O Thin Film Synapse in Neural Network Using LSI", IMFEDK 2018, Jun. (2018)

◆★xSIG:Outstanding M1 Student Award★ 平賀由利亜, 福岡久和, 三谷剛正, 中田尚, 中島康彦: "共有 CNN を用いた高効率な分割推論実行モデル", xSIG 2018: The 2nd. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, Apr. (2018)

◆Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, and Yasuhiko Nakashima: "A Programmable Analog Calculation Unit for Vector Computations", IEEE Symposium on Low-Power and High-Speed Chips 2018, Apr. (2018)

◆Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, and Yasuhiko Nakashima: "EMAXVR: A Programmable Accelerator Employing Near ALU Utilization to DSA", IEEE Symposium on Low-Power and High-Speed Chips 2018, Apr. (2018)

◇Yasuhiko Nakashima: "The End of Normal-computing Era. The Opportunity of Next Computations", International Workshop on Frontiers in Computing Systems and Wireless Communications (FOSCOM 2018), Mar. (2018)

★電子情報通信学会関西支部学生会研究発表講演会奨励賞★ 菊谷雄真, 山野龍佑, 一倉孝宏, 中島康彦: "エッジコンピューティング向けアクセラレータの実装と評価", 電子情報通信学会関西支部第23回研究発表講演会, Mar. (2018)

・菊谷雄真, 山野龍佑, 一倉孝宏, 中島康彦: "時分割多重実行型シストリックリングの実装と評価", 信学技報, vol.117, no.378, CPSY2017-111, pp.31-36, Jan. (2018)

◆Hoang Gia Vu, Takashi Nakada, and Yasuhiko Nakashima: "Efficient Multitasking on FPGA Using HDL-based Checkpointing", 14th International Symposium on Applied Reconfigurable Computing (ARC2018), pp.1-3, May. (2018)

◆Mutsumi Kimura, Yuki Koga, Hiroki Nakanishi, Tokiyoshi Matsuda, Tomoya Kameda, and Yasuhiko Nakashima: "In-Ga-Zn-O Thin-Film Devices as Synapse Elements in a Neural Network", IEEE J. Electron Devices Society, pp.100-105, Apr. (2018)

◆Duc-Phuc NGUYEN, Thi-Hong TRAN, Dinh-Dung LE, Yasuhiko NAKASHIMA: "Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems", International Conference and Exhibition on Visible Light Communications 2018 (ICEVLC2018), Mar. (2018)

◆Hoang-Gia VU, Shinya TAKAMAEDA-YAMAZAKI, Takashi NAKADA, and Yasuhiko NAKASHIMA: "A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing", IEICE Trans., Vol.E101-D, No.2, pp.288-302, Feb. (2018)

◆D.D. Le, D.P., Nguyen, Thi Hong Tran, Y. Nakashima: "Joint Polar and Run-length Limitted Decoding Scheme for Visible Light Communication Systems", IEICE Communications Express Letter, Vol.7, Issue 1, pp.19-24, Jan. (2018)

----2017-----------------------------------------------------------------------------------------------------

◆★1'st Prize in Poster Presentation★ Duc-Phuc Nguyen, Dinh-Dung Le, Dai-Long Hoang, Satoya Yoshida, Thi-Hong Tran, and Yasuhiko Nakashima: "A Precise Indoor Localization System with Fixed Visible Light Communication LEDs for Smart Shopping", IC-TECS2017 (poster), Dec. (2017)

◇中島康彦: "Approximate Computingとシストリックアレイ", ジスクソフト技術講演会, Dec. (2017)

◆Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada and Yasuhiko Nakashima: "Compression and aggregation for optimizing information transmission in distributed CNN", CANDAR'17, REGULAR PAPER, pp.112-118, Nov. (2017)

◆★CANDAR'17 Outstanding Paper Award★ Renyuan Zhang, Takashi Nakada and Yasuhiko Nakashima: "A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing", CANDAR'17, REGULAR PAPER, pp.180-186, Nov. (2017)

・Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima: "A Programmable Analog Calculation Unit based on Support Vector Regression", 信学技報, vol.117, no.314, CPSY2017-55, pp.27-32, Nov. (2017)

・福岡久和, 平賀由利亜, 三谷剛正, 中田尚, 中島康彦: "分散CNNにおける圧縮と集約による情報転送の最適化", 信学技報, vol.117, no.314, CPSY2017-59, pp.51-54, Nov. (2017)

・松山且樹, 藤井政圭, 津邑公暁, 中島康彦: "自動メモ化プロセッサにおける復帰アドレス別の再利用率調査とその応用", 情報処理学会研究報告, Vol.2017-ARC-227, No.19, Jul. (2017)

・福岡久和, 三谷剛正, 平賀由利亜, 中田尚, 中島康彦: "動画圧縮技術を利用した分散機械学習における情報伝達効率化", 信学技報, vol.117, no.153, CPSY2017-30, pp.151-155, Jul. (2017)

◆Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Yasuhiko Nakashima: "NON-RLL DC BALANCE BASED ON NON-SYSTEMATIC POLAR CODE FOR VISIBLE LIGHT COMMUNICATION", Vietnam - Japan Scientific Exchange Meeting 2017 (VJSE2017), Sep. (2017)

◇中島康彦: "Deep Learningに向けたApproximate Computingとシストリックアレイアーキテクチャ", 革新的コンピューティングの研究開発戦略検討会, JST, Jul. (2017)

◇中島康彦: "GoogleのTPUにも使われたシストリックアレイアーキテクチャとDeep Learningについて", 富士通研究所技術講演会, Jul. (2017)

・Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Takashi Nakada, Yasuhiko Nakashima: "A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems", 信学技報, vol.117, no.44, CPSY2017-2, pp.3-7, May. (2017)

・Dinh Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima, Son Kiet Nguyen, Huu Thuan Huynh: "A prototype of Dimmable Visible Light Communication System on FPGA", 信学技報, vol.117, no.44, CPSY2017-3, pp.9-13, May. (2017)

・福岡久和, 山野龍佑, 中島康彦: "各種FPGAによる畳み込み演算向けシストリックリングの実装と評価", CPSY研究会, 2017-05-23, May. (2017)

・山野龍佑, 中島康彦: "時分割多重実行によるシストリックリングの面積効率向上手法", 信学技報, vol.117, no.44, CPSY2017-6, pp.27-32, May. (2017)

・平賀由利亜, 三谷剛正, 福岡久和, 中田　尚, 中島康彦: "エッジコンピューティングによる分散ニューラルネットワークの構想", 信学技報, vol.117, no.44, CPSY2017-11, pp.62-67, May. (2017)

◆Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima: "CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing", FCCM2017 (poster), May. (2017)

◆★xSIG:Outstanding M2 Student Award★ Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "A Multi-Level Power-Capping Mechanism for FPGAs", xSIG 2017: The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, Apr. (2017)

◆Mutsumi KIMURA, Hiroki NAKANISHI, Nao NAKAMURA, Tomoharu YOKOYAMA, Tokiyoshi MATSUDA, Tomoya KAMEDA, and Yasuhiko NAKASHIMA: "Simplification of Processing Elements in Cellular Neural Network", SciTechnol-Journal of Electrical Engineering and Electronic Technology, Apr. (2017)

◆★ICFCC Best Oral Presentation Award★ Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima: "A Multi-mode Error-Correction Solution based on Split-Concatenation for Wireless Sensor Nodes", The 9th International Conference on Future Computer and Communication(ICFCC 2017), Apr. (2017)

◆Mutsumi Kimura, Ryohei Morita Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima: "Cellular neural network formed by simplified processing elements composed of thin-film transistors", Elsevier-Journal Neurocomputing 248, pp.112-119, http://dx.doi.org/10.1016/j.neucom.2016.10.085, Mar. (2017)

◇中島康彦: "99%メモリなアクセラレータIMAX(In Memory Accelerator eXtension)", CAE計算環境研究会@関西シスラボ 第8回シンポジウム, Mar. (2017)

◆Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima: "A Multi-mode Error-Correction Solution based on Split-Concatenation for Wireless Sensor Nodes", Journal of Communications (JCM) Vol.12, No.2, pp.130-136, Doi:10.12720/jcm.12.2.130-136, Feb. (2017)

・一倉孝宏, 山野龍佑, 福岡久和, 中島康彦: "DCNNに最適なCGRAの探索と予備評価", 信学技報, vol.116, no.416, CPSY2016-114, pp.49-54, Jan. (2017)

・Vu Hoang Gia, Takamaeda-Yamazaki Shinya, Nakada Takashi, Nakashima Yasuhiko: "A Framework for Tree-based Checkpointing Architecture for FPGA Computing", IPSJ-SLDM, Jan. (2017)

----2016-----------------------------------------------------------------------------------------------------

◆Yuttakon YUTTAKONKIT, Shinya TAKAMAEDA-YAMAZAKI and Yasuhiko NAKASHIMA: "Performance Optimization of Light-field Applications on GPU", IEICE Trans., Vol.E99-D, No.12, pp.3072-3081, Dec. (2016)

◆Hoang Gia Vu, Shinya Takamaeda, Yasuhiko Nakashima: "CPRtree: A Tree-based Checkpointing Architecture for Heterogeneous FPGA Computing", CANDAR'16, REGULAR PAPER, pp.57-66, Nov. (2016)

◆Yuttakon YUTTAKONKIT, Shinya TAKAMAEDA-YAMAZAKI and Yasuhiko NAKASHIMA: "Performance Comparison of CGRA and Mobile GPU for Light-field Image Processing", CANDAR'16, REGULAR PAPER, pp.174-180, Nov. (2016)

◆Masayoshi FUJII, Yuuki SATO, Tomoaki TSUMURA and Yasuhiko NAKASHIMA: "Exploiting Bloom Filters for Saving Power Consumption of Auto-Memoization Processor", Proc. 4'th Int'l Workshop on Computer Systems and Architectures(CSA16), pp.354-360, Nov. (2016)

◆Keisuke Fujimoto, Shinya Takamaeda, Yasuhiko Nakashima: "Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs", Proc. 4'th Int'l Workshop on Computer Systems and Architectures(CSA16), pp.361-367, Nov. (2016)

◆Hiromasa KATO, Shinya Takamaeda, Yasuhiko Nakashima: "CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis", Proc. 4'th Int'l Workshop on Computer Systems and Architectures(CSA16), pp.375-380, Nov. (2016)

◆Thi Hong Tran, Duc Phuc Nguyen, and Yasuhiko Nakashima: "PER Evaluation of K-min Viterbi Decoder for Wireless Sensors", 10th international conference on Sensing Technology (ICST-2016), Nov. (2016)

◆Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima: "Letter Reproduction Simulator for Hardware Design of Cellular Neural Network consisting of Neurons using Large-Scale Integration Chip and Synapses using On-deposited amorphous In-Ga-Zn-O films", Proc. International Symposium on Nonlinear Theory and its Applications (NOLTA), Nov. (2016)

◆Mutsumi Kimura, Ryohei Morita, Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima: "Letter Reproduction using a Cellular Neural Network consisting of Simplified Neurons and Synapses fabricated by Thin-Film Transistors", Proc. International Symposium on Nonlinear Theory and its Applications (NOLTA), Nov. (2016)

◆Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima: "ASIC Design of A Low-Complexity K-best Viterbi Decoder for IoT Applications", The IEEE APCCAS 2016, the 13th of the biennial Asia Pacific Conference on Circuits and Systems, Oct. (2016)

・亀田友哉,木村睦,中島康彦: "酸化物半導体シナプス素子を用いた自己学習アナログ型ホップフィールドネットワーク", 信学技報, vol.116, no.240, CPSY2016-41, pp.1-2, Oct. (2016)

・加藤大真, トラン ティ ホン, 中島康彦: "FPGAとカメラ画像を用いた802.11ah物理層の動作検証システム", 信学技報, vol.116, no.240, CPSY2016-47, pp.25-26, Oct. (2016)

・嶋谷知, 三谷剛正, 中島康彦: "ライトフィールド動画の符号化配信ソリューションの検討", 信学技報, vol.116, no.240, CPSY2016-48, pp.27-28, Oct. (2016)

◆Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima: "Letter Reprodution Simulator for Hardware Design of Cellular Neural Network using Thin-Film Synapses", The 23rd International Conference on Neural Information Processing (ICONIP2016), Oct. (2016)

◆Mutsumi Kimura, Nao Nakamura, Tomoharu Yokoyama, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima: "Simplification of Processing Elements in Cellular Neural Networks", The 23rd International Conference on Neural Information Processing (ICONIP2016), Oct. (2016)

◆Duc Phuc NGUYEN, Thi Hong TRAN, Yasuhiko NAKASHIMA: "A High Coding-Gain Reduced-Complexity Serial Concatenated Error-Control Coding Solution for Wireless Sensor Network", IEEE International Conference on Signal and Image Processing, Aug. (2016)

・藤井政圭, 佐藤裕貴, 津邑公暁, 中島康彦: "単調性を利用した計算再利用の近似計算への応用", 信学技報, ARC-221, pp.57-62, Aug. (2016)

・中島康彦: "EMAXVにおける複数バースト転送と複数ベクトル演算のオーバラップ手法", 信学技報, CPSY2016-15, pp.71-76, Aug. (2016)

・福岡久和, 山野龍佑, 高前田伸也, 中島康彦: "高位合成ツールを用いたFPGA並列コンピューティングの可能性検討", 信学技報, CPSY2016-26, pp.181-186, Aug. (2016)

・三谷剛正, 嶋谷知, ユッタコンキット ユッタコン, 中島康彦: "レンズ境界部除去によるライトフィールド動画のHEVC圧縮高速化検討", 信学技報, CPSY2016-29, pp.199-204, Aug. (2016)

・藤本啓輔, 高前田伸也, 中島康彦: "電力制約FPGAアクセラレータにおける実行制御手法の検討", 信学技報, CPSY2016-35, pp.257-262, Aug. (2016)

・三谷剛正, 嶋谷知, ユッタコンキットユッタコン, 中島康彦: "ライトフィールド動画に最適なHEVC圧縮アルゴリズムの提案", 信学技報, CPSY2016-6, pp.41-46, May. (2016)

・嶋谷知, 三谷剛正, ユッタコンキットユッタコン, 中島康彦: "GPUを用いたライトフィールド動画のHEVC圧縮高速化手法の検討", 信学技報, CPSY2016-6, pp.47-51, May. (2016)

・藤井政圭, 佐藤裕貴, 津邑公暁, 中島康彦: "Bloomフィルタを用いた自動メモ化プロセッサのハードウェアコスト削減手法", 研究報告システム・アーキテクチャ（ARC）, 2016-ARC-220, pp.1-8, May. (2016)

◆Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima: "Ultra low-complex IEEE 802.11ah Viterbi Decoder for IoT Applications", IEEE Symposium on Low-Power and High-Speed Chips 2016 (poster), Apr. (2016)

◆Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen and Yasuhiko Nakashima: "ASIC Design of MUL-RED Radix-2 Pipeline FFT Circuit for 802.11ah System" IEEE Symposium on Low-Power and High-Speed Chips 2016, Apr. (2016)

・藤本啓輔, 高前田伸也, 中島康彦: "FPGAアクセラレータの動的電力推定手法の検討", 信学技報, CPSY2015-156, pp.259-264, Mar. (2016)

----2015-----------------------------------------------------------------------------------------------------

★CPSY優秀若手講演賞★ 亀田友哉, 木村睦, 中島康彦: "セルラニューラルネットワークのシミュレータ開発と評価", 信学技報, vol.115, no.342, CPSY2015-63, pp.13-18, Dec. (2015)

・中島康彦: "アルゴリズム記述とCGRA実装を統合するC言語フレームワーク", 信学技報, vol.115, no.342, CPSY2015-65, pp.21-26, Dec. (2015)

・菊谷雄真, Tran Thi Hong, 高前田伸也, 中島康彦: "高位合成ツールVivado HLSとPyCoRAMを用いたFPGAアクセラレータの性能比較", 信学技報, vol.115, no.342, CPSY2015-66, pp.27-32, Dec. (2015)

・三谷剛正, Tran Thi Hong, 高前田伸也, 中島康彦: "HEVCを用いたライトフィールドイメージ圧縮伸張の提案", 信学技報, vol.115, no.342, CPSY2015-67, pp.33-38, Dec. (2015)

・金川宗一郎, NGUYEN Dang Hai, Tran Thi Hong, 高前田伸也, 中島康彦: "EEE802.11ah向け省電力化FFT/IFFT回路に関する研究", 無線通信システム研究会（RCS）, Dec. (2015)

・Nguyen Duc Phuc, Tran Thi Hong, Takamaeda Shinya, Yasuhiko Nakashima: "BER/PER Performance of 802.11ah K-best Viterbi Decoder on Fading Channel", 無線通信システム研究会（RCS）, Dec. (2015)

・Thi Hong Tran, Dwi Rahma Ariyani, Lina Alfaridah ZH, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "Performance Evaluation of K-best Viterbi Decoder for IoT Applications", 信学技報, vol.115, no.342, CPSY2015-70, pp.51-56, Dec. (2015)

★電子情報通信学会コンピュータシステム研究会優秀若手デモ/ポスタ賞★ 嶋谷知, 加藤大真, 亀田友哉, 藤本啓輔, 竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "OculusRiftとメニコアシミュレータによる計算ボトルネック可視化システム", 信学技報, vol.115, no.243, CPSY2015-46, pp.5-6, Oct. (2015)

・竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "低消費電力CGRA EMAXのZynqを用いた実機評価", 信学技報, vol.115, no.243, CPSY2015-51, pp.39-41, Oct. (2015)

◆Tomoya KAMEDA, Mutsumi KIMURA, Yasuhiko NAKASHIMA: "Character Recognition System using Cellular Neural Network suitable for integration on Electronic Displays", Proc. 22nd Int'l Display Workshops(IDW22), Dec. (2015)

◆Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda, Yasuhiko Nakashima: "A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations", Proc. 3rd Int'l Workshop on Computer Systems and Architectures(CSA15), pp.378-384, Dec. (2015)

◆Yuuki Sato, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima: "An Approximate Computing Stack based on Computation Reuse", Proc. 3rd Int'l Workshop on Computer Systems and Architectures(CSA15), pp.385-391, Dec. (2015)

◆Thi Hong Tran, Hiromasa Kato, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications", International Conference on Advanced Technologies for Communications 2015 (ATC'15), Ho Chi Minh city, Oct. (2015)

・Yuttakon Yuttakonkit, Tran Thi Hong, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima: "Design Space Exploration of Computational Photography Accelerator", 信学技報CPSY2015-17 SwoPP論文集, pp.7-12, Aug. (2015)

★情報処理学会システム・アーキテクチャ研究会若手奨励賞★ 枝元正寛, Tran Thi Hong, 高前田伸也, 中島康彦: "ニアメモリ処理アーキテクチャのFPGAへの実装と評価", 信学技報CPSY2015-18 SwoPP論文集, pp.41-46, Aug. (2015)

・竹内昌平, Tran Thi Hong, 高前田伸也, 中島康彦: "Zynqを用いたARM-EMAX密結合アクセラレータの評価", 信学技報CPSY2015-19 SwoPP論文集, pp.47-52, Aug. (2015)

・佐藤裕貴, 津村高範, 津邑公暁, 中島康彦: "自動メモ化プロセッサにおける再利用率向上のための入力値比較手法", 信学技報2015-ARC-216 SwoPP論文集, pp.121-128, Aug. (2015)

◆Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima: "Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators", IEICE Trans., Vol.E98-D, No.12, pp.2141-2149, Dec. (2015)

◆Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima: "A CGRA-based Approach for Accelerating Convolutional Neural Networks", 9th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15) Turin, Italy, Sep.23-25, (2015)

・Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima: "A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications", 信学技報, Vol.115, No.109, RECONF2015-15, pp.79-84, Jun. (2015)

・竹内昌平, TRAN Thi Hong, 高前田伸也, 中島康彦: "グラフ処理向けCGRA in Cacheの提案", 信学技報CPSY2015-7, pp.37-41, Apr. (2015)

・金川宗一郎, TRAN Thi Hong, 高前田伸也, 中島康彦: "GPS付なくしもの探知機プロトタイプ開発", 信学技報CPSY2015-15, pp.83-88, Apr. (2015)

・枝元正寛, TRAN Thi Hong, 高前田伸也, 中島康彦: "非定型計算を高速化するニアメモリ処理アーキテクチャ", 信学技報CPSY2015-9, pp.49-52, Apr. (2015)

◆★IEEE Symposium on Low-Power and High-Speed Chips 2015 Featured Poster Award★ Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima: "A Parameterized Many Core Simulator for Design Space Exploration", IEEE Symposium on Low-Power and High-Speed Chips 2015 (poster), Apr. (2015)

◆Jun Yao, Yasuhiko Nakashima, Kazutoshi Kobayashi, Makoto Ikeda, Wei Xue, Tomohiro Fujiwara, Ryo Shimizu, Masakazu Tanomoto, Yangtong Xu, Xinliang Wang, Weimin Zheng: "XStenciler: a 7.1GFLOPS/W 16-Core Coprocessor with a Ring Structure for Stencil Applications", IEEE Symposium on Low-Power and High-Speed Chips 2015 (poster), Apr. (2015)

◆Anna Zhang, Jun Yao, Yasuhiko Nakashima: "Lowering the Complexity of k-means Clustering by BFS-dijkstra method for Graph Computing", IEEE Symposium on Low-Power and High-Speed Chips 2015, Apr. (2015)

◆Takumi Tsuzuki, Yuko Hara, Shigeru Yamashita, Yasuhiko Nakashima: "Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation", Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Mar. (2015)

----2014-----------------------------------------------------------------------------------------------------

・竹内昌平, 高前田(山崎)伸也, 姚駿, 中島康彦: "次世代アプリケーションのための包括的なアーキテクチャ探索環境の検討", 信学技報CPSY2014-89, pp.25-27, Dec. (2014)

・枝元正寛, 高前田伸也, 姚駿, 中島康彦: "データムービングボトルネックを解決するためのインテリジェントメモリシステムの検討", 信学技報CPSY2014-91, pp.31-33, Dec. (2014)

・平野竜洋, 高前田伸也, 姚駿, 中島康彦: "Triangle Countingのための大規模グラフ分割手法", 信学技報CPSY2014-73, pp.7-12, Nov. (2014)

・紅林修斗, 高前田伸也, 姚駿, 中島康彦: "最短経路探索の並列化と各種プラットホームによる性能比較", 信学技報CPSY2014-74, pp.13-18, Nov. (2014)

・清水怜, 田ノ元正和, 高前田(山崎)伸也, 姚駿, 中島康彦: "メモリネットワークベースアクセラレータの試作と評価", 信学技報CPSY2014-81, pp.51-56, Nov. (2014)

・田ノ元正和, 高前田(山崎)伸也, 姚駿, 中島康彦: "メモリネットワークベースアクセラレータを用いた畳み込みニューラルネットワーク処理", 信学技報CPSY2014-82, pp.57-62, Nov. (2014)

◆Jun Yao, Mitsutoshi Saito, Shogo Okada, Kazutoshi Kobayashi, and Yasuhiko Nakashima: "EReLA: a Low-Power Reliable Coarse-Grained Reconfigurable Architecture Processor and Its Irradiation Tests", IEEE Transactions on Nuclear Science, Vol.61, No.6, pp.3250-3257, DOI=10.1109/TNS.2014.2367541, Dec. (2014)

◆Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka: "A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor", IEEE Micro, pp.54-63, Issue 6, Dec. (2014)

◆Takanori TSUMURA, Yuuki SHIBATA, Kazutaka KAMIMURA, Tomoaki TSUMURA, Yasuhiko NAKASHIMA: "Hinting for Auto-Memoization Processor based on Static Binary Analysis", Proc. 2nd Int'l Workshop on Computer Systems and Architectures (CSA'14), held in conjunction with CANDAR'14, Shizuoka, Japan, pp.426-432, Dec. (2014)

◆Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima: "Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators", Proc. 2nd Int'l Workshop on Computer Systems and Architectures (CSA'14), held in conjunction with CANDAR'14, Shizuoka, Japan, pp.388-393, Dec. (2014)

◆Yuuki Shibata, Takanori Tsumura, Tomoaki Tsumura and Yasuhiko Nakashima: "An Implementation of Auto-Memoization Mechanism on ARM-based Superscalar Processor", Proc. Int'l Symp. on System-on-Chip 2014 (SoC2014), Tampere, Finland, pp.1-8, DOI=10.1109/ISSOC.2014.6972435, Oct. (2014)

・高前田(山崎)伸也，枝元正寛，姚駿，中島康彦: "PyCoRAMを用いたグラフ処理FPGAアクセラレータ", 信学技報CPSY2014-10, pp.1-6, Jul. (2014)

・清水怜，高前田(山崎)伸也，姚駿，中島康彦: "メモリインテンシブアレイアクセラレータを用いた高性能グラフ処理", 信学技報CPSY2014-11, pp.7-12, Jul. (2014)

・小池和正，高前田(山崎)伸也，姚駿，中島康彦: "ニューラルネットワーク処理のエラー削減に向けた命令実行手法", 信学技報CPSY2014-33, pp.137-142, Jul. (2014)

・津村高範，柴田裕貴，神村和敬，津邑公暁，中島康彦: "実行バイナリの静的解析による自動メモ化プロセッサの高速化", 情処研報, 2014-ARC-211, pp.1-9, Jul. (2014)

◆Jun YAO, Yasuhiko NAKASHIMA, Naveen DEVISETTI, Kazuhiro YOSHIMURA, Takashi NAKADA: "A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction", IEICE Trans., Vol.E97-D, No.12, pp.3092-3100, Dec. (2014)

◆Yukihiro SASAGAWA, Jun YAO, Yasuhiko NAKASHIMA: "Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults", IEICE Trans., Vol.J97-D, No.12, pp.3083-3091, Dec. (2014)

・都築匠, 原祐子, 山下茂, 中島康彦: "PPCにおけるLUT挿入位置最適化の定量的評価", DAシンポジウム, Aug. (2014)

・Oliver Kaltstein, Takamaeda Shinya, Jun YAO, Yasuhiko Nakashima: "DIVA-EMIN: Efficient Dependability for Post-Silicon Materials", 平成24年度情報処理学会関西支部大会講演論文集, Sep. (2014)

◆Tanvir Ahmed, Jun Yao, and Yasuhiko Nakashima: "A Two-Order Increase in Robustness of Partial Redundancy Under a Radiation Stress Test by Using SDC Prediction", IEEE Transactions on Nuclear Science, Vol.61, Issue.4, pp.1567-1574, DOI=10.1109/TNS.2014.2314691, Aug. (2014)

◆Jun Yao, Mitsutoshi Saito, Shogo Okada, Kazutoshi Kobayashi, and Yasuhiko Nakashima: "EReLA: a Low-Power Reliable Coarse-Grained Reconfigurable Architecture Processor and Its Irradiation Tests", IEEE Nuclear and Space Radiation Effects Conference 2014 (poster), Jul. (2014)

◆★IEEE Symposium on Low-Power and High-Speed Chips 2014 Featured Poster Award★ Masakazu Tanomoto, Jun Yao, Yasuhiko Nakashima, Yangtong Xu, Xinliang Wang, Wei Xue: "Performance Tuning of a Global Shallow-water Atmospheric Model on Xeon Phi", IEEE Symposium on Low-Power and High-Speed Chips 2014 (poster), Apr. (2014)

◆Shuto Kurebayashi, Jun Yao, Yasuhiko Nakashima: "A Pipelined Newton-Raphson Method for Floating Point Division and Square Root on Distribted Memory CGRAs", IEEE Symposium on Low-Power and High-Speed Chips 2014 (poster), Apr. (2014)

◆Tatsuhiro Hirano, Jun Yao, Yasuhiko Nakashima: "Tuning of a Breadth First based Triangle-counting by using Multi-threading", IEEE Symposium on Low-Power and High-Speed Chips 2014 (poster), Apr. (2014)

◆Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima: "A Globally Asynchronous Locally Synchronous DMR Architecture for Aggressive Low-Power Fault Toleration", IEEE Symposium on Low-Power and High-Speed Chips 2014, Apr. (2014)

◆Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka: "A Flexibly Fault-Tolerant FU Array Processor and its Self-Tuning Scheme to Locate Permanently Defective Unit", IEEE Symposium on Low-Power and High-Speed Chips 2014, Apr. (2014)

◆Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima: "Better-than-DMR techniques for Yield Improvement", FCCM-2014, May. (2014)

・Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima: "An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration", 情報処理学会研究報告. 計算機アーキテクチャ研究会報告, 2014-ARC-209(9), 1-7, Mar. (2014)

◆Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima: "Novel Area-Efficient Technique for Yield Improvement", Workshop on Design Automation for Understanding Hardware Designs, Design Automation and Test in Europe (DATE), Mar. (Electronic) (2014)

・林大地, 藤原知広, 姚駿, 中島康彦: "演算器アレイ型アクセラレータへのメモリインテンシブなアプリケーションの写像と性能評価", 情報処理学会研究報告, 計算機アーキテクチャ研究会報告, 2014-ARC-208(17), 1-5, Jan. (2014)

・楠田浩平, 姚駿, 中島康彦: "メモリ分散型アレイアクセラレータのための命令生成手法の開発と評価", 情報処理学会研究報告, 計算機アーキテクチャ研究会報告, 2014-ARC-208(16), 1-7, Jan. (2014)

◆Yuko HARA-AZUMI, Masaya KUNIMOTO, and Yasuhiko NAKASHIMA: "Emulator-Oriented Tiny Processors for Unreliable Post-Silicon Devices: A Case Study", ASP-DAC, 19th Asia and South Pacific Design Automation Conference, pp.85-90, Jan. (2014)

----2013-----------------------------------------------------------------------------------------------------

◆Yuuki SHIBATA, Kazutaka KAMIMURA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "CAM Size Reduction Method for Auto-Memoization Processor by considering Characteristics of Loops", Proc. 1st Int'l Workshop on Computer Systems and Architectures (CSA'13), held in conjunction with CANDAR'13, REGULAR PAPER, pp.378-384, Dogo Spa, Japan, Dec. (2013)

★SLDM研究会優秀発表学生賞★ 早苗駿一, 原祐子, 山下茂, 中島康彦: "PPCに基づく高歩留まり回路の発見的設計手法", 情報処理学会 デザインガイア, VLD2013-65, Vol.113, No.320, pp.27-32, 鹿児島, Nov. (2013)

◆Tanvir AHMED, Jun YAO, and Yasuhiko NAKASHIMA: "A Two-Order Increase in Robustness of Partial Redundancy Under Radiation Stress Test by Using SDC Prediction", In 2013 IEEE Conference on Radiation Effects on Components and Systems (RADECS), C-7, pp.1-7, Sep. (2013)

・中島康彦: "超軽量センサを実現するプリンタブルコンピュータの構想", 第1回STARCワークショップ, Sep. (2013)

・早苗駿一, 原祐子, 山下茂, 中島康彦: "Partially-Programmable Circuit の歩留まり向上のためのLUT 最適化手法", 情報処理学会 DAシンポジウム, pp.27-32, 下呂, Aug. (2013)

・稲垣慶和, 原祐子, 姚駿,中島康彦: "リング型アレイアクセレータ向け演算ライブラリの実装と性能評価", 研究報告計算機アーキテクチャ（ARC）, 2013-ARC-206, No.1, pp.1-6, Jul. (2013)

・林大地, 関賀, 原祐子, 姚駿,中島康彦: "メモリ分散型アレイアクセラレータの浮動小数点演算に関する性能考察", 研究報告計算機アーキテクチャ（ARC）, 2013-ARC-206, No.8, pp.1-6, Jul. (2013)

・藤原知広, 姚駿, 原祐子, 中島康彦: "リング型アレイアクセラレータのマクロパイプライン化による性能見積もり", 研究報告計算機アーキテクチャ（ARC）, 2013-ARC-206, No.14, pp1-6, Jul. (2013)

・柴田裕貴, 神村和敬, 津邑公暁, 松尾啓志, 中島康彦: "再利用表パージアルゴリズムの改良による自動メモ化プロセッサのハードウェア削減手法", 研究報告計算機アーキテクチャ（ARC）, 2013-ARC-206, No.15, pp1-9, Jul. (2013)

★CPSY優秀若手講演賞★ 國本将也, 原祐子, 中島康彦: "永久故障回避のための等価命令列置換手法", 信学技報, Vol.113, No.169, CPSY2013-30, pp.121-126, Jul. (2013)

・森高晃大, 吉田浩章, 伴野充,中島康彦: "コヒーレントキャッシュを用いたSoCのシステム設計技法", 信学技報, Vol.113, No.30, VLD2013-10, pp.73-78, May. (2013)

◆Tanvir AHMED, Jun YAO, Yuko HARA-AZUMI, Shigeru YAMASHITA, and Yasuhiko NAKASHIMA: "Selective Check of Data-Path for Effective Fault Tolerance", IEICE Trans., Vol.J96-D, No.8, pp.1592-1601, Aug. (2013)

◆Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, and Weimin Zheng: "HW/SW Approaches to Accelerate GRAPES in an FU Array", IEEE Symposium on Low-Power and High-Speed Chips 2013, Apr. (2013)

◆大上俊, 姚駿, 中島康彦: "演算器アレイにおける高信頼化命令写像手法", IEICE Trans., Vol.J96-D, No.3, pp.472-483, Mar. (2013)

◇中島康彦: "LSI化に繋がるシミュレータ開発手法と設計事例", 計算機アーキテクチャ研究会, Mar. (2013)

・Hao Xu, Yuko Hara-Azumi, Yasuhiko NAKASHIMA: "Comparison of emulation oriented 8-bit ISA with 6502 ISA for an ARM emulator", 研究報告計算機アーキテクチャ(ARC), 2013-ARC-204 No.9, Mar. (2013)

・王昊，姚駿，中島康彦: "GCCのvectorizerを利用した演算器アレイ向け命令変換手法", 研究報告計算機アーキテクチャ(ARC), 2013-ARC-203 No.9, Feb. (2013)

・関賀，姚駿，中島康彦: "リング接続を利用しデータ移動を最小限にするアクセラレータの提案", 研究報告システムLSI設計技術（SLDM）SIG Technical Reports, 2013-SLDM-159, Vol.17, pp.1-6, Jan. (2013)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima: "Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication", IEICE Trans., Vol.E96-D, No.1, pp.1-8, Jan. (2013)

----2012-----------------------------------------------------------------------------------------------------

◆★ICNC'12 Best Paper Award★ Kazutaka KAMIMURA, Ryosuke ODA, Tatsuhiro YAMADA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "A Speed-Up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions", Proc. 3rd Int'l. Conf. on Networking and Computing (ICNC'12), LONG PAPER, Okinawa, Japan, pp.49-57, (Dec. 2012) (doi: 10.1109/ICNC.2012.17) Dec. (2012)

◆Jun YAO, Shogo Okada, Masaki Masuda, Kazutoshi Kobayashi, Yasuhiko Nakashima: "DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and its Case Study of Radiation Stress Test", IEEE Transactions on Nuclear Science, Vol.59, Issue.6, pp.2852-2858, DOI=10.1109/TNS.2012.2223715, Dec. (2012)

・中島康彦: "フィルムコンピュータ実現に向けたエミュレータ専用小型CPUの検討", 信学技報CPSY2012-12 SwoPP論文集, pp.19-24, Aug. (2012)

・山中良祐, 姚駿, 中島康彦: "セレクタ部に着目した演算器アレイ型アクセラレータの高信頼化手法", 信学技報CPSY2012-13 SwoPP論文集, pp.25-30, Aug. (2012)

・Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima: "Achieving Near-Optimal Dependability with Minimal Hardware Costs in an FU Array Pro-cessor by Soft Error Rate Monitoring", 研究報告計算機アーキテクチャ（ARC）,2012-ARC-201(4),1-6, Aug. (2012)

・神村和敬, 山田龍寛, 小田遼亮, 津邑公暁, 松尾啓志, 中島康彦: "再利用対象区間の細分化による自動メモ化プロセッサの高速化", 研究報告計算機アーキテクチャ（ARC）,2012-ARC-201(16),1-8, Aug. (2012)

・大谷友哉, Tanvir Ahmed, 姚駿, 中島康彦: "演算器アレイにおける冗長化オーバヘッドの少ない高信頼化手法の提案", 研究報告計算機アーキテクチャ（ARC）,2012-ARC-201(19),1-6, Aug. (2012)

◆Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, Yasuhiko NAKASHIMA: "RazorProtector: Maintaining Razor DVS Efficiency in Large IR-drop Zones by an Adaptive Redundant Data-Path", IEICE Trans. on VLSI Design and CAD Algorithms, Vol.E95-A, No.12, pp.2319-2329, Dec. (2012)

◆Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima: "Introducing OVP Awareness to Achieve an Efficient Permanent Defect Locating", NANOARCH 2012, pp.43-49, Netherlands, Jul. (2012)

・YAO Jun，NAKASHIMA Yasuhiko: "Deep DVS in FU array by Covering Process Variations with Data-Path Auto-fix", 研究報告計算機アーキテクチャ（ARC）, Vol.2012-ARC-200, No.18, pp.1-9, May. (2012)

◆齊藤光俊, 下岡俊介, Devisetti Venkatarama Naveen, 大上俊, 吉村和浩, 姚駿, 中田尚, 中島康彦: "線形演算器アレイ型アクセラレータを備えた高電力効率プロセッサの開発", 電子情報通信学会論文誌D, Vol.J95-D, No.9, pp.1729-1737, Sep. (2012)

◆岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "時分割実行機構による演算器アレイ型アクセラレータの効率化", 情報処理学会論文誌コンピューティングシステム, ACS39, Vol.5, No.4, pp.13-23, Aug. (2012)

◆Jun YAO, Shogo Okada, Hajime Shimada, Kazutoshi Kobayashi and Yasuhiko Nakashima: "DARA: a Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test", 2012 IEEE Nuclear and Space Radiation Effects Conference, Jul. (2012)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima: "Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication", TAMC2012 (2012)

◆吉村和浩, 中田尚, 中島康彦, 北村俊明: "異種命令セットアーキテクチャを持つ高電力効率SMT プロセッサの開発", 電子情報通信学会論文誌D, Vol.J95-D, No.6, pp.1334-1346, Jun. (2012)

◆中田尚, 吉村和浩, 下岡俊介, 大上俊, Devisetti Venkatarama Naveen, 中島康彦: "画像処理向け線形アレイアクセラレータの性能評価", 情報処理学会論文誌コンピューティングシステム, ACS38, Vol.5, No.3, pp.74-85, May. (2012)

・王昊, 姚駿, 中島康彦: "多様なアクセスパターンに適応するアクセラレータ向けメモリアクセス機構", IPSJ SIG Notes 2012-ARC-199(15), pp.1-4, 2012-03-20, 長崎, Mar. (2012)

・Tanvir Ahmed, Jun Yao and Yasuhiko Nakashima: "Achieving Effective Fault Tolerance in FU array by Adding AVF Awareness", IPSJ SIG Notes 2012-ARC-199(5), pp.1-4, 2012-03-20, 長崎, Mar. (2012)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum Walks on the Line with Phase Parameters", IEICE Trans. on Foundations of Computer Science, Vol.E95-D, No.3, pp.722-730, Mar. (2012)

----2011-----------------------------------------------------------------------------------------------------

◆Yukihiro SASAGAWA, Jun YAO, Takashi NAKADA, Yasuhiko NAKASHIMA: "Improving DVS Efficiency by Tolerating IR-drops with an Adaptive Redundant Data-Path", WRA 2011 : 2nd Workshop on Resilient Architectures (in conjuction with MICRO-2011), Dec. (2011)

・森高晃大, 下岡俊介, 吉村和浩, 姚駿, 中田尚, 中島康彦: "大規模演算器アクセラレータのための複数FPGA連結手法", IEICE technical report. Computer systems 111(328), 9-14, 2011-11-22, デザインガイア2011, Nov. (2011)

・齊藤光俊, 下岡俊介, 吉村和浩, 姚駿, 中田尚, 中島康彦: "演算器アレイ型アクセラレータの実装とその分析", IEICE technical report. Computer systems 111(328), 9-14, 2011-11-22, デザインガイア2011, Nov. (2011)

・村田絵理, 大竹哲史, 中島康彦: "組込み自己テストにおける温度均一化制御", デザインガイア2011, DC(62), Nov. (2011)

・狹間洋平, 姚駿, 中田尚, 中島康彦: "二重化を用いた演算器アレイにおける故障箇所特定手法", IEICE technical report. Computer systems 111(328), 47-52, 2011-11-22, デザインガイア2011, Nov. (2011)

◇中島康彦: "高性能・低電力・高信頼を全部満たす次世代コンピュータはこんな姿？", けいはんな情報通信研究フェア2011, Nov. (2011)

◇中島康彦: "汎用プロセッサと相性の良い演算器アレイ型アクセラレータの構想", ICD第3回アクセラレーション技術発表討論会, テーマ：アクセラレータ技術の展開を目指して, Sep. (2011)

◆Ryosuke ODA, Tatsuhiro YAMADA, Tomoki IKEGAYA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "Input Entry Integration for an Auto-Memoization Processor", Proc. of The 3rd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS), Osaka, pp.179-185, Nov. (2011)

・笹川幸宏, 姚駿, 中田尚, 中島康彦: "演算器の適応的冗長化による高効率DVS 方式の提案", 信学技報, vol.111, no.164, DC2011-15, pp.1-6, Jul. (2011)

・山田龍寛, 小田遼亮, 池谷友基, 津邑公暁, 松尾啓志, 中島康彦: "命令区間の特徴を用いた自動メモ化プロセッサの再利用率向上手法", 研究報告計算機アーキテクチャ（ARC）,2011-ARC-196(1), pp.1-7, Jul. (2011)

・小田遼亮, 山田龍寛, 池谷友基, 津邑公暁, 松尾啓志, 中島康彦: "自動メモ化プロセッサの入力値エントリ統合による高速化", 研究報告計算機アーキテクチャ（ARC）,2011-ARC-196(2), pp.1-10, Jul. (2011)

・下岡俊介, 吉村和浩, 中田尚, 中島康彦: "演算器アレイ型アクセラレータにおけるローカルバッファの最適化", 研究報告計算機アーキテクチャ（ARC）,2011-ARC-196(18), pp.1-6, Jul. (2011)

・大上俊, 吉村和浩, 姚駿, 中田尚, 中島康彦: "演算器アレイにおける高信頼化命令写像手法", 研究報告計算機アーキテクチャ（ARC）,2011-ARC-196(19), pp.1-7, Jul. (2011)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum Query Complexity of Hamming Distance Estimation", Proc. of Asian Conference on Quantum Information Science, AQIS, pp.103-104, Aug. (2011)

◆Tomoki IKEGAYA, Ryosuke ODA, Tatsuhiro YAMADA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "A Hybrid Model of Speculative Execution and Scout Threading for Auto-Memoization Processor", Proc. of Int'l. Symp. on System-on-Chip 2011 (SoC2011), Tampere, Finland, pp.22-28, Nov. (2011)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum Query Complexity of Hamming Distance Estimation", 8th Canadian Student Conference on Quantum Information Science, Montreal, Canada, Jun. (2011)

◆Jun YAO, Ryoji WATANABE, Kazuhiro YOSHIMURA, Takashi NAKADA, Hajime SHIMADA, Yasuhiko NAKASHIMA: "An Efficient and Reliable 1.5-way Processor by Fusion of Space and Time", WDSN11, pp.69-74, Jun. (2011)

◆Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima: "LAPP: A Low Power Array Accelerator with Binary Compatibility", HPPAC2011, pp.849-857, May. (2011)

◆岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "仮想化機構による演算器アレイ型アクセラレータの効率化", 先進的計算基盤システムシンポジウムSACSIS2011論文集, pp.136-143, May. (2011)

◆森浩大，大上俊，下岡俊介，吉村和浩，中田尚，中島康彦: "演算器アレイ型アクセラレータのための命令変換手法", 先進的計算基盤システムシンポジウムSACSIS2011論文集(ポスター), 11-608, pp.207-208, May. (2011)

・YAO Jun, Yasuhiko NAKASHIMA: "EReLA: Exploiting Efficiency of Redundant Executions on an FU array", 情報処理学会研究報告, Vol.2011-ARC-194(9), pp.1-5, Mar. (2011)

◆Kazuhiro YOSHIMURA, Takuya IWAKAMI, Takashi NAKADA, Jun YAO, Hajime SHIMADA and Yasuhiko NAKASHIMA: "An Instruction Mapping Scheme for FU Array Accelerator", IEICE Trans. on Information and Systems, Vol.E94-D, No.2, pp.286-297, Feb. (2011)

◇中島康彦: "プログラムモデルを維持しつつ大幅な高性能・低電力化を可能とするプロセッサアーキテクチャ", 第18回＜けいはんな＞新産業創出交流センターシーズフォーラム, Jan. (2011)

◆Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "An Efficient Conversion of Quantum Circuits to a Linear Nearest Neighbor Architecture", Quantum Information and Computation, Vol.11, No.1&2, pp.141-166 (2011)

----2010-----------------------------------------------------------------------------------------------------

★電子情報通信学会集積回路研究会優秀若手研究ポスター賞★ 大上俊, 岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "アレイ型アクセラレータにおける演算器間ネットワークの設計", 集積回路研究会(ICD), Dec. (2010)

・下岡俊介, 岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "演算器アレイ型アクセラレータにおけるメモリアクセス機構の設計", 集積回路研究会(ICD), Dec. (2010)

・岩上拓矢, 吉村和浩, 森浩大, 中田尚, 中島康彦: "演算器アレイを拡張する細粒度時分割機構", 集積回路研究会(ICD), Dec. (2010)

★情報処理学会関西支部大会学生奨励賞★ 渡邊良二, 姚駿, 中田尚, 嶋田創, 中島康彦: "サイクルレベルの空間及び時間冗長化技術を融合させた高信頼プロセッサの提案", 平成22年度情報処理学会関西支部大会講演論文集, A-05, Sep. (2010)

◆J.Yao, R.Watanabe, T.Nakada, H.Shimada, Y.NAKASHIMA, K.Kobayashi: "A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors", 16th Pacific Rim International Symposium on Dependable Computing (PRDC'10), pp.237-238, Dec. (2010)

◆★ICNC'10 Best Paper Award★ Tomoki IKEGAYA, Tomoaki TSUMURA, Hiroshi MATSUO, Yasuhiko NAKASHIMA: "A Speed-up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations (regular paper)", Proc. 1st Int'l. Conf. on Networking and Computing (ICNC'10), pp.63-70, Higashi-Hiroshima, Japan, Nov. (2010)

・森浩大, 岩上拓矢, 吉村和浩, 中田尚, 中島康彦: "演算器アレイ型アクセラレータのための命令変換手法の検討", SWoPP2010(Vol.2010-ARC-190 No.26 2010/8/4), pp.1-6, Aug. (2010)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima: "Asymptotics of Quantum Walks on the Line with Phase Parameters", 10th Asian Conference on Quantum Information Science (poster), Aug.27-31 (2010)

◆Daisuke Yokomine, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima: "A SAT Solver Based on Quantum and Classical Random Walk", 10th Asian Conference on Quantum Information Science (poster), Aug.27-31 (2010)

◆池谷友基, 津邑公暁, 松尾啓志, 中島康彦: "複数イタレーションの一括再利用による並列事前実行の高速化, 情報処理学会論文誌コンピューティングシステム(ACS), Vol.3, No.3, pp.31-43, Sep. (2010)

◆池谷友基, 津邑公暁, 松尾啓志, 中島康彦: "自動メモ化プロセッサにおける複数イタレーションの一括再利用", 先進的計算基盤システムシンポジウムSACSIS2010論文集, pp.149-156, May. (2010)

◆岩上拓矢, 吉村和浩, 上利宗久, 中田尚, 中島康彦: "プログラマビリティを備える低電力アクセラレータの提案と評価", 先進的計算基盤システムシンポジウムSACSIS2010論文集(poster), May. (2010)

◆Takuya Iwakami, Munehisa Agari, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima: "Area Optimization of FU Array in Low-Power Accelerators", IEEE Symposium on Low-Power and High-Speed Chips 2010 (poster), Apr. (2010)

・吉村和浩, 上利宗久, 中田尚, 中島康彦: "演算器アレイ型プロセッサのための命令スケジューラの設計と評価", 信学技報, Vol.109, No.474, pp.511-516, Mar. (2010)

★SLDM研究会優秀発表学生賞★ 大賀健司, 姚駿, 中田尚, 嶋田創, 山下茂, 中島康彦: "少品種高信頼セルを用いた高信頼回路設計手法と信頼性評価手法の提案", 信学技報, Vol.109, No.474, pp.139-146, Mar. (2010)

◆Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima, Toshiaki Kitamura: "An Energy Efficient SMT Processor with Heterogeneous Instruction Set Architectures", IASTED Int'l Conf. on Parallel and Distributed Computing and Networks (PDCN2010), pp.201-209, Feb. (2010)

◆柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦: "量子計算の並列シミュレーションにおける通信量削減手法", 電子情報通信学会論文誌D, Vol.J93-D, No.3, pp.1-12 (2010)

----2009-----------------------------------------------------------------------------------------------------

◆Yushi Kamiya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima: "A Speculative Technique for Auto-Memoization Processor with Multithreading", PDCAT 2009, pp.160-166, Dec. (2009)

・中田尚, 中島康彦: "線形アレイVLIWプロセッサにおける適応性検討", 情報処理学会研究報告, Vol.2009-ARC-186, No.10, HOKKE-17, pp.1-9, Nov. (2009)

★情報処理学会関西支部大会学生奨励賞★ 上利宗久, 中田尚, 中島康彦: "線形アレイ型VLIWプロセッサの面積効率評価", 平成21年度情報処理学会関西支部大会講演論文集, A-03, Sep. (2009)

・大賀健司, 中田尚, 嶋田創, 山下茂, 中島康彦: "二線式論理を用いた面積効率の良い高信頼演算器", 平成21年度情報処理学会関西支部大会講演論文集, A-07, Sep. (2009)

◇中島康彦: "グリーンコンピューターへの道～計算の低消費電力化～", 関西学研都市６大学市民講座, Oct. (2009)

・Jun Yao,Hajime Shimada,Takashi Nakada,Yasuhiko Nakashima: "A Light Bypass Network Design for Cascading ALU Executions", IPSJ SIG Technical Reports, 2009-ARC-184, pp.1-9, Aug. (2009)

・Antti Vikman, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita,Yasuhiko Nakashima: "An efficient middle-level framework for quantum circuit simulation on multiple simulator platforms", IEICE Technical Report CPSY2009, pp.25-30, Aug. (2009)

◆Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum Walks on the Line with Phase Parameters", International Conference on Quantum Information and Technology (ICQIT2009), Dec. (2009)

◆中田尚, 片岡晶人, 中島康彦: "VLIW型命令キューを持つスーパースカラプロセッサの命令スケジューリング機構", 情報処理学会論文誌コンピューティングシステム, ACS26, Vol.2, No.2, pp.48-62, Jul. (2009)

◆中田尚, 上利宗久, 中島康彦: "画像処理向け線形アレイVLIWプロセッサ", 先進的計算基盤システムシンポジウムSACSIS2009論文集, pp.293-300, May. (2009)

★IEEE SSCS Japan Chapter Academic Research Award★ 吉村和浩, 市来亮人, 中田尚, 中島康彦: "異種命令混在実行プロセッサOROCHIの開発", 電子情報通信学会LSIとシステムのワークショップ2009 (poster), May. (2009)

◆Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima: "A Linear Array VLIW Processor for Image Processing", IEEE Symposium on Low-Power and High-Speed Chips 2009 (poster), p.153, Apr. (2009)

◆Kazuhiro Yoshimura, Takashi Nakada and Yasuhiko Nakashima: "An Instruction Decomposition Method for Reconfigurable Decoders", IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA2009 post proceeding), Mar. (2009)

◇中島康彦: "脱マルチコアの試み －ヘテロSMT型VLIWとリニアアレイ型VLIW－", 情報処理学会ものづくり基盤コンピューティングシステム研究会招待講演, Mar. (2009)

◆Y.Nakajima, Y.Kawano, H.Sekigawa, M.Nakanishi, S.Yamashita, and Y.Nakashima: "Synthesis of Quantum Circuits for d-Level Systems by using Cosine-Sine Decomposition", Quantum Information & Computation, Vol.9, No.5&6, pp.423-443 (2009)

◆Y.Hirata, M.Nakanishi, S.Yamashita, and Y.Nakashima: "An Efficient Method to Convert Arbitrary Quantum Circuits to Ones on a Linear Nearest Neighbor Architecture", Proc. of the Third International Conference on Quantum, Nano and Micro Technologies(ICQNM 2009), Feb. (2009)

----2008-----------------------------------------------------------------------------------------------------

◇中島康彦: "３－ｗａｙから９Ｎ－ｗａｙに至る最近のＶＬＩＷ研究紹介", 電子情報通信学会コンピュータシステム研究会招待講演, CPSY, Vol.2008 No.43-52, pp.31-36, Dec. (2008)

◆Kazunori SUZUKI, Takashi NAKADA, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA: "A Functional Unit with Small Variety of Highly Reliable Cells", 14th Pacific Rim International Symposium on Dependable Computing (PRDC'08), pp.353-354, Dec. (2008)

◆Takashi Nakada, Yasuhiko Nakashima, Hajime Shimada, Kenji Kise, Toshiaki Kitamura: "OROCHI: A Multiple Instruction Set SMT Processor", First International Workshop on New Frontiers in High-performance and Hardware-aware Computing(HipHaC'08), pp.1-8, Nov. (2008)

◇中島康彦: "ステレオ画像処理システムの構築と高速化", 日本テクノセンターセミナー, Nov. (2008)

・洪勇基, 中西正樹, 山下茂, 中島康彦: "FPGAのスイッチマトリクスを対象とするソフトエラー対策", IEICE Technical Report RECONF2008-45, pp.39-44, Nov. (2008)

・堀田敬一, 中田尚, 中西正樹, 山下茂, 中島康彦: "高信頼セルによる回路の信頼性評価", IEICE Technical Report VLD2008-75, pp.91-96, Nov. (2008)

・市来亮人, 吉村和浩, 中田尚, 中島康彦: "異種命令SMTプロセッサOROCHIのASIC試作における問題と対策", 平成20年度情報処理学会関西支部大会講演論文集, pp.13-16, Oct. (2008)

・上利宗久, 中田尚, 中島康彦: "Ｎ倍速を目指すＶＬＩＷプロセッサの構想", IPSJ SIG Technical Report, 2008-ARC-180, pp21-24, Oct. (2008)

・吉村和浩, 中田尚, 中島康彦: "異種命令SMTプロセッサOROCHIの実装と分析", SWoPP2008, pp.1-6, Aug. (2008)

・神谷優志, 島崎裕介, 新美明仁, 津邑公暁, 松尾啓志, 中島康彦: "複数スレッドを用いた自動メモ化プロセッサのオーバヘッド削減手法", SWoPP2008, pp.109-114, Aug. (2008)

・鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦: "高信頼セルによる演算器の耐故障性と遅延時間の評価", SWoPP2008, pp.181-186, Aug. (2008)

・Y. Hirata, M. Nakanishi, S. Yamashita, and Y. Nakashima: "An Efficient Method to Convert Arbitrary Quantum Circuits to Ones on a Linear Nearest Neighbor Architecture," IEICE Technical Report, QIT2008-57, pp.45-50, Nov. (2008)

・柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦: "並列量子計算シミュレータにおける通信料削減手法の提案", 第18回量子情報技術研究会資料, QIT2008-41, pp.180-183, May (2008)

・柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦: "量子計算の並列シミュレーションにおける通信量削減手法", SWoPP2008, pp.133-138, Aug. (2008)

◆島崎裕介, 津邑公暁, 中島浩, 松尾啓志, 中島康彦: "エネルギー制御を備える自動メモ化プロセッサ", 情報処理学会論文誌:コンピューティングシステム, ACS23, pp.1-11, Aug. (2008)

・北村俊明, 中島康彦: "異種命令セットを同時に実行するマルチスレッディング・プロセッサの研究", STARCフォーラム/シンポジウム, ポスター, Jul. (2008)

・吉村和浩: "異種命令混在実行プロセッサにおけるQoS制御", STARCフォーラム/シンポジウム 学生ポスター, Jul. (2008)

・市來亮人: "プロセッサ評価のためのハイブリッドプラットホーム", STARCフォーラム/シンポジウム 学生ポスター, Jul. (2008)

◆島崎裕介, 津邑公暁 ,中島浩, 松尾啓志, 中島康彦: "エネルギー制御を備える自動メモ化プロセッサ", 先進的計算基盤システムシンポジウムSACSIS2008論文集, pp.57-64, Jun. (2008)

◆Akihito Ichiki, Takashi Nakada, Yasuhiko Nakashima: "A Hybrid Platform for Practical Evaluation of Processors", IEEE Symposium on Low-Power and High-Speed Chips 2008 (poster), Apr. (2008)

◆Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima: "A QoS Control Method for a Heterogeneous SMT Processor", IEEE Symposium on Low-Power and High-Speed Chips 2008 (poster), Apr. (2008)

・鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦: "少品種高信頼セルによる演算器の提案と評価", 信学技報, vol.107, no.559, DC2007-112, pp.167-172, Mar. (2008)

・牟田口公洋, 中田尚, 中島康彦: "パイプラインプロセッサ上でのMIN-TAGE予測器の性能評価", IPSJ SIG Technical Report, HOKKE2008, pp.37-42, Mar. (2008)

・山原幹雄, 中田尚, 中島康彦: "異種命令混在実行プロセッサにおけるプロセススケジューリング手法", IPSJ SIG Technical Report, HOKKE2008, pp.73-78, Mar. (2008)

・村上ユミコ, 中西正樹, 萩原学, 山下茂, 中島康彦: "量子状態を送信するための量子秘匿直接通信とその安全性", 暗号と情報セキュリティシンポジウム(SCIS2008), 2D1-1, Jan. (2008)

◇中島康彦: "ステレオ画像処理の基礎とその応用 -高速化と低電力化をプロセッサアーキテクチャから考える-", 日本テクノセンターセミナー, Jan. (2008)

----2007-----------------------------------------------------------------------------------------------------

・中田尚, 中島康彦: "異種命令混在実行のためのVLIW型命令キューの設計", IPSJ SIG Technical Report, 2007-ARC-175, pp89-94, Nov. (2007)

・鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦: "細粒度命令分解と少品種セルによる高信頼化アーキテクチャの提案", IPSJ SIG Technical Report, 2007-ARC-175, pp61-66, Nov. (2007)

・里山宏平, 中田尚, 中西正樹, 山下茂, 中島康彦: "SRAMベースFPGAにおける耐ソフトエラーLUT構成法", IEICE Technical Report, RECONF2007-43, pp.1-6, Nov. (2007)

・片岡晶人, 中田尚, 中島康彦: "アウトオブオーダー実行におけるマルチバンク構成レジスタファイルの評価", 平成19年度情報処理学会関西支部大会講演論文集, pp.121-124, Oct. (2007)

◆Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "Synthesis of quantum circuits for d-level systems using KAK decomposition", The 11th Workshop on Quantum Information Processing Dec. (2007)

◇中島康彦: "マルチコアの光と影, だまされないための基礎知識", SONY社内向け先端技術講座, Nov. (2007)

◇中島康彦: "コンピュータの目が危険を知らせる -超高速/低電力コンピュータへの挑戦-", 奈良先端大学院公開講座2007, Nov. (2007)

◇中島康彦: "異種命令セット同時実行プロセッサOROCHIの開発", 情報処理学会関西支部システムLSI研究会招待講演, Sep. (2007)

・新美明仁, 池内康樹, 鈴木郁真, 津邑公暁, 松尾啓志, 中島康彦: "並列化および再利用によるGAの高速化", SWoPP2007, Aug (2007)

・島崎裕介, 池内康樹, 鈴木郁真, 津邑公暁, 松尾啓志, 中島康彦: "自動メモ化プロセッサの低消費エネルギー化", SWoPP2007, Aug (2007)

・須賀圭一, 山原幹雄, 中田尚, 中島康彦: "異種命令セットを同時に実行するマルチスレッディング・プロセッサの構成", SWoPP2007, pp.17-22, Aug. (2007)

★論文賞＋船井ベストペーパー賞★ 島崎裕介, 池内康樹, 津邑公暁, 中島浩, 松尾啓志, 中島康彦: "自動メモ化プロセッサの消費エネルギー評価", FIT 2007 第6回情報科学技術フォーラム, pp.51-54, Jul. (2007)

◇中島康彦: "ステレオ画像処理の基礎とその応用 -高速化と低電力化をプロセッサアーキテクチャから考える-", 日本テクノセンターセミナー, Apr. (2007)

◆Y. Murakami, M. Nakanishi, M. Hagiwara, S. Yamashita, and Y. Nakashima: "A quantum secure direct communication protocol for sending a quantum state and its security analysis", The Tenth Workshop on Quantum Information Processing (QIP 2007), January (2007)

◆Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, and Yasuhiko Nakashima: "A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads", International Workshop on Applied Reconfigurable Computing (ARC2007) pp.343-349 (2007)

・片岡晶人, 中西正樹, 山下茂, 中島康彦: "VLIW型命令キューを持つOROCHIの命令スケジューリング機構", 情処研報, 2007-ARC-172, pp.25-30, Mar. (2007)

◆Tomoaki Tsumura, Ikuma Suzuki, Yasuki Ikeuchi, Hiroshi Matsuo, Hiroshi Nakashima, Yasuhiko Nakashima: "Design and Evaluation of An Auto-Memoization Processor", PDCN 2007, pp.245-250, Feb. (2007)

◆Hajime Shimada, Takashi Shimada, Takekazu Tabata, Tomoya Kojima, Kenji Kise, Yasuhiko Nakashima, Toshiaki Kitamura: "Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor", IWIA pp.110-117 (2007)

----2006-----------------------------------------------------------------------------------------------------

◆Yumiko Murakami, Masaki Nakanishi, Manabu Hagiwara, Shigeru Yamashita, Yasuhiko Nakashima: "Quantum secure direct communication protocols for sending a quantum state", Proc. of the 2006 International Symposium on Infromation Theory and its Applications, ISITA (2006)

◆Hiroyuki Nishiyama, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: "An efficient approximation of SU(d) using decomposition", Proc. of Asian Conference on Quantum Information Science, AQIS (2006)

・小島知也, 中島康彦: "OROCHI評価用集中命令ウィンドウ型スーパスカラの設計", 情処研報, 2006-ARC-170, pp.61-66, Nov. (2006)

・J. Yao, H. Shimada, Y. Nakashima, S. Mori, S. Tomita: "An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption", IPSJ SIG Technical Reports, 2006-ARC-170, pp.43-48, Nov. (2006)

◆Y.Yoshimura, K.Saito, H.Shimada, S.Miwa, Y.Nakashima, S.Mori, S.Tomita: "Three Quads: An Interconnection Network for Interactive Simulations", System Modeling and Simulation Theory and Applications, Asia Simulation Conf., pp362-366 (2006)

◆三輪忍, 福山智久, 島田創, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "パス情報を用いた分岐フィルタ機構", 情報処理学会論文誌:コンピューティングシステム, ACS15, pp.108-118, Sep. (2006)

◇中島康彦: "マルチコアを想定した動的区間投機および区間再利用の試み", 第18回STARCアドバンスト講座 システムアーキテクチャセミナー -システムアーキテクチャの新しい要素技術-, pp.133-149, Jul. (2006)

◆J. Yao, H. Shimada, Y. Nakashima, S. Mori, S. Tomita: "Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption", ISHPC 2005 and ALPS 2006, LNCS 4759, pp.494-507 (2006)

・福山智久, 三輪忍, 島田創, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "スラック予測を用いたクラスタ型スーパスカラ・プロセッサ向け命令ステアリング", 情処研報, 2006-ARC-169, pp.55-60, Aug. (2006)

・Jun Yao, Hajime Shimada, Yasuhiko Nakashima, Shinichiro Mori, Shinji Tomita: "Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection", IPSJ SIG Technical Reports, 2006-ARC-168, pp.19-24, Jun. (2006)

・中島康彦: "ARMアーキテクチャ向け命令分解型スーパスカラ", 情処研報, 2006-ARC-168, pp.77-82, Jun. (2006)

◆高山征大, 森眞一郎, 中島康彦, 富田眞治: "セル投影型並列ボリュームレンダリングのEarly Ray Terminationによる高速化", 情報処理学会論文誌:コンピューティングシステム, ACS14, pp.124-136, May. (2006)

◆三輪忍, 福山智久, 島田創, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "パス情報を用いた分岐フィルタ機構", 先進的計算基盤システムシンポジウムSACSIS2006論文集, pp.315-323, May. (2006)

・池内康樹, 鈴木郁真, 津邑公暁, 中島康彦, 中島浩: "再利用における連想記憶の必要容量および管理アルゴリズムの評価", 情処研報, 2006-ARC-167 (HOKKE2006), pp.211-216, Mar. (2006)

◇中島康彦: "コンピュータ・アーキテクチャに関わったこれまでの２０年, これからの２０年", 奈良先端科学技術大学院大学 特別講演会, Feb. (2006)

----2005-----------------------------------------------------------------------------------------------------

・中島康彦: "命令レベル並列がダメなら, 命令を減らせ！", JST「情報基盤と利用環境」領域平成17年度研究報告会要旨集, Dec. (2005)

・嶋田創, 森眞一郎, 中島康彦, 富田眞治: "大規模パイプラインステージ統合 -CPU内部からチップセットまで-", 情処研報, 2005-ARC-165 (デザインガイア), pp.63-66, Nov. (2005)

・高洪波, 李森, 中島康彦, 嶋田創, 森眞一郎, 富田眞治: "並列事前実行における再利用バッファの高速化", 情処研報, 2005-ARC-165 (デザインガイア), pp.27-32, Nov. (2005)

・李森, 高洪波, 中島康彦, 富田眞治: "区間再利用バッファの分割と高速化", 平成17年度情報処理学会関西支部大会講演論文集, pp.181-182, Oct. (2005)

・高洪波, 李森, 中島康彦, 嶋田創, 森眞一郎, 富田眞治: "並列事前実行における連想検索装置の設計", 平成17年度情報処理学会関西支部大会講演論文集, pp.183-186, Oct. (2005)

◆鈴木郁真, 池内康樹, 津邑公暁, 中島康彦, 中島浩: "再利用によるGAの高速化手法", 情報処理学会論文誌:コンピューティングシステム, ACS12, pp.129-143, Dec. (2005)

◆中島康彦, 五島正裕, 森眞一郎, 富田眞治: "外部連想バッファを備えるSpMTモデルの分析", 先進的計算基盤システムシンポジウムSACSIS2005論文集, pp.397-406, May. (2005)

◆福山智久, 福田正則, 三輪忍, 小西将人, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "スラック予測を用いた省電力アーキテクチャ向け命令スケジューリング", 先進的計算基盤システムシンポジウムSACSIS2005論文集, pp.123-132, May. (2005)

◆鈴木郁真, 池内康樹, 津邑公暁, 中島康彦, 中島浩: "GAにおける再利用の評価", 先進的計算基盤システムシンポジウムSACSIS2005論文集, pp.133-141, May. (2005)

・鈴木郁真, 池内康樹, 津邑公暁,中島康彦, 中島浩: "再利用を用いたGAの高速化", 情処研報 2005-ARC-154/2005-HPC-101 (HOKKE2005), Mar. (2005)

----2004-----------------------------------------------------------------------------------------------------

・津邑公暁, 中島康彦, 中島浩: "並列事前実行機構におけるループカウンタ予測", 情処研報 2004-ARC-160, pp.83-88, Dec. (2004)

◆丸山悠樹, 中田智史, 高山征大, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "汎用グラフィックスカードを用いた並列ボリュームレンダリングシステム", 情報処理学会論文誌:コンピューティングシステム, ACS7, pp.332-345, Nov. (2004)

◆MUJAHID Alam, KAKUSHO Koh, MINOH Michihiko, NAKASHIMA Yasuhiko, MORI Shin-ichiro, TOMITA Shinji: "Parallel Cloth Simulation with Adaptive Mesh Refinement and Coarsening Using OpenMP on Fujitsu HPC2500", 情報処理学会論文誌:コンピューティングシステム, ACS7, pp.312-331, Nov. (2004)

◆Takayama, M., Mori, S., Shinomoto, Y., Goshima, M., Nakashima, Y. and Tomita, S.: "Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing", Int'l Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA 2004), pp.373-379 (2004)

◆Takayama, M., Mori, S., Shinomoto, Y., Goshima, M., Nakashima, Y. and Tomita, S.: "Cell-Projection Parallel Volume Rendering with Early Ray Termination", Int'l Conf. on Visualization, Imaging and Image Processing (VIIP 2004), pp.613-618 (2004)

◆額田匡則, 小西将人, 五島正裕, 中島康彦, 富田眞治: "参照の空間局所性を最大化するボリューム・レンダリング・アルゴリズムの改良", 情報処理学会論文誌:コンピューティングシステム, ACS7, pp.356-367, Nov. (2004)

・清水雄歩, 笠原寛壽, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "汎用CAMを用いた区間再利用プロセッサシミュレータの高速化", 平成16年度情報処理学会関西支部大会講演論文集, pp.175-178, Oct. (2004)

・清水雄歩, 笠原寛壽, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "汎用CAMを用いた区間再利用プロセッサシミュレータの高速化", 信学技報CPSY2004-16 SwoPP論文集, pp.43-48, Jul. (2004)

◆丸山悠樹, 中田智史, 高山征大, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "汎用グラフィックスカードを用いた並列ボリュームレンダリングシステム", 先進的計算基盤システムシンポジウムSACSIS2004論文集, pp.415-424, May. (2004)

◆MUJAHID Alam, KAKUSHO Koh, MINOH Michihiko, NAKASHIMA Yasuhiko, MORI Shin-ichiro, TOMITA Shinji: "Parallel Cloth Simulation with Adaptive Mesh Refinement and Coarsening Using OpenMP on Fujitsu HPC2500", 先進的計算基盤システムシンポジウムSACSIS2004論文集, pp.397-406, May. (2004)

◆額田匡則, 小西将人, 五島正裕, 中島康彦, 富田眞治: "参照の空間局所性を最大化するボリューム・レンダリング・アルゴリズムの改良", 先進的計算基盤システムシンポジウムSACSIS2004論文集, pp.305-314, May. (2004)

◆劉小路, 小西将人, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "クリティカリティ予測のためのスラック予測", 先進的計算基盤システムシンポジウムSACSIS2004論文集, pp.187-196, May. (2004)

◆津邑公暁, 笠原寛壽, 清水雄歩, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "大容量汎用3値CAMを用いた並列事前実行機構の効率的実現", 先進的計算基盤システムシンポジウムSACSIS2004論文集, pp.251-259, May. (2004)

・笠原寛壽, 清水雄歩, 津邑公暁, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "2次キャッシュを用いた再利用および並列事前実行機構における高速化手法", 情処研報 2004-ARC-157/2004-HPC-97 (HOKKE2004), pp.133-138, Mar. (2004)

◆Mujahid, A., Kakusho, K., Minoh, M., Nakashima, Y., Mori, S., Tomita, S.: "Simulating Realistic Force and Shape of Virtual Cloth with Adaptive Meshes and Its Parallel Implementation in OpenMP", IASTED Int'l Conf. on Parallel and Distributed Computing and Networks (PDCN2004), pp.386-391, Feb. (2004)

◆津邑公暁, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "並列事前実行機構における主記憶値テストの高速化", 情報処理学会論文誌:コンピューティングシステム, ACS4, pp.31-42, Jan. (2004)

----2003-----------------------------------------------------------------------------------------------------

・三輪忍, 永野貴宣, 五島正裕, 中島康彦, 富田眞治: "リカレントネットにおける移動ロボットのナビゲーション課題の学習", 平成15年度情報処理学会関西支部大会 講演論文集, pp.181-184, Oct. (2003)

・高山征大, 丸山悠樹, 木下 純, 森眞一郎, 津邑公暁, 五島正裕, 中島康彦, 富田眞治: "非構造格子ボリュームデータの可視化における動的負荷分散", 平成15年度情報処理学会関西支部大会 講演論文集, pp.179-180, Oct. (2003)

・丸山悠樹, 高山征大, 木下 純, 津邑公暁, 五島正裕, 中島康彦, 森眞一郎, 富田眞治: "実時間インタラクティブシミュレーションのための遅延隠蔽手法", 平成15年度情報処理学会関西支部大会 講演論文集, pp.177-178, Oct. (2003)

・丸山悠樹, 中田智史, 高山征大, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "汎用グラフィックスカードを用いた並列ボリュームレンダリングシステムの実装", 情報処理学会研究報告(2003-ARC-154), Vol.2003, No.84, pp.61-66, Aug. (2003)

・高山征大, 森眞一郎, 津邑公暁, 五島正裕, 中島康彦, 富田眞治: "大規模ボリュームレンダリング処理における疑似透視投影法に関する考察", 可視化情報学会第31回可視化情報シンポジウム, pp.381-384, Jul. (2003)

◆Alam MUJAHID, Koh KAKUSHO, Michihiko MINOH, Yasuhiko NAKASHIMA, Shin-ichiro MORI and Shinji TOMITA: "Comparison Between Adaptive Refinement and Adaptive Coarsening for Simulating Realistic Force and Shape of Virtual Cloth", MMU Int'l Symp. on Information and Communications Technologies (M2USIC2003) (2003)

・森眞一郎, 生雲公啓, 高山征大, 丸山悠樹, 津邑公暁, 五島正裕, 中島康彦, 富田眞治: "大規模データの並列可視化を支援するFPGA搭載PCIカード", 第１回リコンフィギャラブルシステム研究会論文集, pp.15-20, Sep. (2003)

・津邑公暁, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "汎用CAMを用いた既存プログラム高速化手法の提案", 第１回リコンフィギャラブルシステム研究会論文集, pp.21-26, Sep. (2003)

◆津邑公暁, 清水雄歩, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "ステレオ画像処理を用いた曖昧再利用の評価", 情報処理学会論文誌:コンピューティングシステム, ACS3, pp.246-256, Sep. (2003)

◆清水雄歩, 津邑公暁, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "距離画像生成処理におけるメディアプロセッサの評価", 情報処理学会論文誌:コンピューティングシステム, ACS3, pp.257-267, Sep. (2003)

◆額田匡則, 小西将人, 五島正裕, 中島康彦, 富田眞治: "参照の空間局所性を最大化するボリューム・レンダリング・アルゴリズム", 情報処理学会論文誌:コンピューティングシステム, ACS3, pp.137-146, Sep. (2003)

◆S. Mori, T. Tsumura, M. Goshima, Y. Nakashima, H. Nakashima, S. Tomita: "ReVolver/C40: A Scalable Parallel Computer for Volume Rendering", IEICE Trans. on Information and Systems, Vol.E86-D, No.10, pp.2006-2015 (2003)

◆中島康彦, 津邑公暁, 五島正裕, 森眞一郎, 富田眞治: "動的命令解析に基づく多重再利用および並列事前実行", 情報処理学会論文誌:コンピューティングシステム, ACS2, pp.1-16, Jul. (2003)

◆額田匡則, 小西将人, 五島正裕, 中島康彦, 富田眞治: "参照の空間局所性を最大化するボリューム・レンダリング・アルゴリズム", 先進的計算基盤システムシンポジウムSACSIS2003論文集, pp.333-340, May. (2003)

◆津邑公暁, 清水雄歩, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "ステレオ画像処理を用いた曖昧再利用の評価", 先進的計算基盤システムシンポジウムSACSIS2003論文集, pp.97-104, May. (2003)

◆森眞一郎, 中田智史, 高山征大, 丸山悠樹, 生雲公啓, 津邑公暁, 五島正裕, 中島康彦, 富田眞治: "大規模ボリュームデータの並列可視化環境の構築--専用ハードウェアを用いた実装--", 先進的計算基盤システムシンポジウムSACSIS2003論文集(ポスターセッション), pp.165-166, May. (2003)

・竹村尚大, 津邑公暁, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "曖昧再利用によるMP3エンコーダの高速化手法", 情報処理学会研究報告, ARC-152-25, pp.145-150, Mar. (2003)

・中島康彦: "経済学部における基礎情報処理教育教材の開発", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１４年度研究成果報告書, pp.615-622, Mar. (2003)

・津邑公暁, 清水雄歩, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "曖昧再利用によるステレオ画像処理の高速化", 情報処理学会研究報告, ARC-151-7, pp.37-42, Jan. (2003)

----2002-----------------------------------------------------------------------------------------------------

・生雲公啓, 高山征大, 丸山悠樹, 中田智史, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "サイクリックにデータを配置した並列ボリュームレンダリング処理における ERT の効果", 情報科学技術フォーラム(FIT2002), Vol.3, pp.233-234, Sep. (2002)

・生雲公啓, 高山征大, 丸山悠樹, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "実時間インタラクティブシミュレーションのための並列ボリュームレンダリング環境", 平成14年度情報処理学会関西支部大会, pp.121-124, Nov. (2002)

・清水雄歩, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "VLIW型メディアプロセッサを用いたステレオ画像処理の評価", 平成14年度情報処理学会関西支部大会, pp.119-120, Nov. (2002)

・尼嵜央典, 中島康彦, 五島正裕, 森眞一郎, 富田眞治: "SPARCアーキテクチャにおける関数値再利用機構の改良", 平成14年度情報処理学会関西支部大会, pp.115-116, Nov. (2002)

・原瀬史靖, 山内聡, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 北村俊明, 富田眞治: "数値シミュレーション過程の実時間可視化を支援するハードウェア", 可視化情報学会第30回可視化情報シンポジウム, Jul. (2002)

・小西将人, 小田累, 西野賢悟, 五島正裕, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "直接依存行列型スケジューリングを適用したクラスタ化スーパースケーラ・プロセッサの評価", 情報処理学会研究報告, ARC-149-26, Aug. (2002)

◆Damien Le Moal, 生雲公啓, 五島正裕, 森眞一郎, 中島康彦, 北村俊明, 富田眞治: "Priority Enhanced Stride Scheduling", 情報処理学会論文誌:ハイパフォーマンスコンピューティングシステム, HPS5, pp.99-111, Sep. (2002)

◆五島正裕, 西野賢悟, 小西将人, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "行列に基づくOut-of-Orderスケジューリング方式の評価", 情報処理学会論文誌:ハイパフォーマンスコンピューティングシステム, HPS5, pp.13-23, Sep. (2002)

◆中島康彦, 緒方勝也, 正西申悟, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "関数値再利用および並列事前実行による高速化技術", 情報処理学会論文誌:ハイパフォーマンスコンピューティングシステム, HPS5, pp.1-12, Sep. (2002)

・中島康彦: "経済学部における基礎情報処理教育の現状 －３年目を迎えて－", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１４年度第１回領域全体会議, Jul. (2002)

・原瀬史靖, 山内聡, 森眞一郎, 津邑公暁, 五島正裕, 中島康彦, 北村俊明, 富田眞治: "ReVolver/C40を用いた時系列ボリュームデータの実時間可視化", 情報処理学会研究報告, ARC-148-2, pp.7-12, May. (2002)

◆木村篤彦, 中島康彦, 宮田佳昭, 中川伸二, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "低電力Javaプロセッサのための投機的クロック制御", 情報処理学会論文誌, Vol.43, No.6, pp.1956-1967 (2002)

◆中島康彦, 緒方勝也, 正西申悟, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "関数値再利用および並列事前実行による高速化技術", 並列処理シンポジウムJSPP2002論文集, pp.269-276, May. (2002)

◆小西将人, 小田累, 西野賢悟, 五島正裕, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "クラスタ化スーパースケーラ・プロセッサにおける直接依存行列型スケジューリング方式", 並列処理シンポジウムJSPP2002論文集, pp.19-26, May. (2002)

◆五島正裕, 西野賢悟, 小西将人, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "行列に基づくOut-of-Orderスケジューリング方式の評価", 並列処理シンポジウムJSPP2002論文集, pp.11-18, May. (2002)

・中島康彦: "経済学部における基礎情報処理教育教材の開発", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１３年度研究成果報告書, pp.333-339, Mar. (2002)

・緒方勝也, 正西申悟, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "関数値再利用および並列事前実行による高速化技術の提案と評価", 情報処理学会研究報告, ARC-147-28, pp.163-168, Mar. (2002)

・中島康彦: "経済学部における基礎情報処理教育教材の開発", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１３年度第２回領域全体会議, Jan. (2002)

----2001-----------------------------------------------------------------------------------------------------

◆Masahiro Goshima, Kengo Nishino, Yasuhiko Nakashima, Shin-ichiro Mori and Shinji Tomita: "A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors", Proc. 34th Annual Int'l Symp. on Microarchitecture (MICRO-34), pp.225-236 (2001)

◆Damien Le Moal, Mineyoshi Masuda, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Toshiaki Kitamura and Shinji Tomita: "Priority Enhanced Stride Scheduling", Int'l Conf. on High Perfomance Computing in the Asia-Pacific Region, Online Proceedings (2001)

◆★情報処理学会論文賞★ 五島正裕, 西野賢悟, グエン ハイハー, 縣 亮慶, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "スーパースケーラのための高速な動的命令スケジューリング方式", 情報処理学会論文誌:ハイパフォーマンスコンピューティングシステム, HPS3, pp.77-92, Aug. (2001)

・西野賢悟, 五島正裕, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "スーパースケーラのための高速な動的命令スケジューリング方式のIPCの評価", 情報処理学会研究報告, ARC-144-30, pp.171-176, Aug. (2001)

・山内聡, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 北村俊明, 富田眞治: "透視投影ボリュームレンダリングにおけるサンプリング方式の評価", 画像電子学会第29回年次大会予稿集, pp.33-34, Aug. (2001)

・山内聡, 津邑公暁, 五島正裕, 森眞一郎, 中島康彦, 北村俊明, 富田眞治: "アクティブボリュームレンダリングに基づくシミュレーションステアリング", 電子通信学会技術報告, CPSY2001-35, pp.1-8, Aug. (2001)

◆西野賢悟, 五島正裕, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "スーパースケーラのための高速な動的命令スケジューリング方式の改良", 並列処理シンポジウムJSPP2001論文集, pp.137-138, Jun. (2001)

◆山田克樹, 尼嵜央典, 中島康彦, 五島正裕, 森眞一郎, 北村俊明, 富田眞治: "Javaバイトコード実行におけるデータ再利用の分析", 並列処理シンポジウムJSPP2001論文集, pp.173-180, Jun. (2001)

・中島康彦: "経済学部における基礎情報処理教育教材の開発", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１２年度研究成果報告書, pp.195-198, Mar. (2001)

・五島正裕, 西野賢悟, グエン ハイハー, 縣 亮慶, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "スーパースケーラのための高速な命令スケジューリング方式", 情報処理学会研究報告, ARC-142-21, pp.121-126, Mar. (2001)

・木村篤彦, 中島康彦, 宮田佳昭, 中川伸二, 北村俊明, 五島正裕, 森眞一郎, 富田眞治: "低電力化のための投機的クロック供給制御", 情報処理学会研究報告, ARC-142-4, pp.19-24, Mar. (2001)

◆五島正裕, グェンハイハー, 縣亮慶, 中島康彦, 森眞一郎, 北村俊明, 富田眞治: "Dualflowアーキテクチャの命令発行機構", 情報処理学会論文誌, Vol.42, No.4, pp.652-662 (2001)

----2000-----------------------------------------------------------------------------------------------------

・中島康彦: "経済学部におけるUNIXおよびC演習の現状", 高等教育改革に資するマルチメディアの高度利用に関する研究, 平成１２年度第１回領域全体会議, Oct. (2000)

・縣 亮慶, グエン ハイハー, 五島正裕, 森眞一郎, 中島康彦, 富田眞治: "Superscalarにおける低遅延な命令スケジューリング方式", 情報処理学会研究報告, ARC-139-19, pp.109-114, Aug. (2000)

・グエン ハイハー, 五島正裕, 縣 亮慶, 中島康彦, 森眞一郎, 富田眞治: "Dualflowアーキテクチャの命令発行機構", 情報処理学会研究報告, ARC-139-18, pp.103-108, Aug. (2000)

・山田克樹, 中島康彦, 富田眞治: "投機的手法を用いたデータ再利用によるJava仮想マシンの高速化", 情報処理学会研究報告, ARC-139-29, pp.169-174, Aug. (2000)

・中島康彦: "Java仮想マシンの高速化の可能性", 京都大学経済学会・経済論叢, Vol.165, No.3, pp.1-28, Mar. (2000)

◆重田大助, 小川洋平, 山田克樹, 中島康彦, 富田眞治: "命令畳み込み, データ投機および再利用技術を用いたJava仮想マシンの高速化", 情報処理学会論文誌:ハイパフォーマンスコンピューティングシステム, HPS1, pp.28-38, Aug. (2000)

・重田大助, 小川洋平, 山田克樹, 中島康彦, 富田眞治: "命令畳み込み, データ投機および再利用技術を用いたJava仮想マシンの高速化", 情報処理学会研究報告, ARC-137-3, pp.13-18, Mar. (2000)

----1997-----------------------------------------------------------------------------------------------------

◆中島康彦, 上埜治彦, 田尻邦彦, 鈴木貴朗: "動的命令変換手法によるMアーキテクチャ・エミュレーション", 情報処理学会論文誌, Vol.38, No.11, pp.2309-2320 (1997)

◆中島康彦, 大野優人, 竹部好正: "VPP500スカラプロセサの性能", 情報処理学会論文誌, Vol.38, No.4, pp.863-872 (1997)

----1995-----------------------------------------------------------------------------------------------------

◆Nakashima Y., Kitamura T., Tamura H., Takiuchi M., Miura K.: "Scalar Processor of the VPP500 Parallel Supercomputer", Proc. of 9th ACM Int. Conf. of Supercomputing, pp.348-356, Jul. (1995)

----1994-----------------------------------------------------------------------------------------------------

・中島康彦, 北村俊明, 田村秀夫, 滝内政昭: "VPP500スカラプロセッサの特徴", 富士通株式会社研究成果発表会 (1994)

・中島康彦, 北村俊明, 田村秀夫, 滝内政昭: "VPP500スカラプロセッサの特徴", 情報処理学会研究報告, ARC-104-17, pp.129-136, Jan. (1994)

----1989-----------------------------------------------------------------------------------------------------

◆中島康彦, 新實治男, 柴山潔, 萩原宏: "3次元形状モデリングにおける立体集合演算の並列処理方式", 情報処理学会論文誌, Vol.30, No.10, pp.1298-1308 (1989)

----1986-----------------------------------------------------------------------------------------------------

・中島康彦, 新實治男, 富田眞治, 萩原宏: "実時間3次元動画システムにおける動画記述", jus UNIXシンポジウム (1986)

★情報処理学会学術奨励賞★ 中島康彦, 新實治男, 富田眞治, 萩原宏: "実時間3次元動画システムにおける動画記述", 第33回情報処理学会全国大会論文集, 2Q-2, pp.2073-2074 (1986)

----1984-----------------------------------------------------------------------------------------------------

・"カオス・シミュレーション", Oh!PC, No 4, pp.90, 1984.

----1983-----------------------------------------------------------------------------------------------------

・"High Speedグラフィックルーチン", Oh!PC, No 12, pp.192-193, 1983.

・"ナノピコ教室解答", bit, Vol 15, No 2, pp.206, 1983.

著書

●共著 中島康彦ほか: "IoT・AIを利活用したヘルスモニタリング（9章 エッジコンピューティング計算基盤の研究開発", テクノシステム, 2020.

●編著 中島康彦: "OHM大学テキストシリーズ第38巻 コンピュータアーキテクチャ", オーム社, 2012.

●共著 富田眞治ほか: "大学生の新教養科目情報社会とコンピュータ（9章 データ構造とアルゴリズム担当）", 昭晃堂, 2005.

●単著 中島康彦: "C言語で「やりたい」ことを「できる」にかえる基本の12章", メディアテック出版, 2001.

●単著 中島康彦: "UNIXで「やりたい」ことを「できる」にかえる基本の12章", メディアテック出版, 2000.

Yasuhiko NAKASHIMA received B.E., M.E., and Ph.D. degrees in Computer Engineering from Kyoto University in 1986, 1988, and 1998, respectively. From 1988 to 1999, he was an engineer in the computer divisions of FUJITSU Limited, where he worked on parallel vector supercomputers, emulation technologies, and high-speed CMOS circuits. From 1999 to 2005, he was an associate professor in the Graduate School of Economics, Kyoto University, conducting research on high-performance processors and computational reuse. Since 2006, he has been a professor in the Graduate School of Science and Technology at the Nara Institute of Science and Technology (NAIST). In 2024, he co-founded LENZO Inc., where he serves as Chief Architect. His research interests include computer architecture, reconfigurable computing, CGRA/CGLA-based heterogeneous systems, AI and edge accelerators, near-memory computing, neuromorphic and stochastic computing, and reliable, low-power systems. He is a fellow of IEICE and a senior member of IEEE.